• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2000년도 추계 기술심포지움 논문집
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• pp.23-27
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• 2000

Simultaneous Switching Noise (SSN) propagated through parallel power and ground planes in high-speed multilayer printed circuit boards (PCBs) causes malfunction of both digital and analog circuits. To reduce SSN, decoupling capacitors are generally used in the PCBs. In this paper, we improve the equivalent circuit model of decoupling capacitor in high-frequency range to analyze the effect of SSN reduction accurately. The analysis is performed by the microwave and RF design system (MDS) method and the finite difference time domain (FDTD) method. We compared the results by the ideal capacitor model with those by the proposed model.

• Journal of information and communication convergence engineering
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• 제9권1호
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• pp.11-15
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• 2011

A Differential line inductor is proposed for a differential power amplifier. The proposed differential line inductor is composed of two conventional line inductors rearranged to make the current direction of the two line inductors identical. The proposed line inductor is simulated with a 2.5-D and a 3-D EM simulator to verify its feasibility with the substrate information in a 0.18-${\mu}m$ RF CMOS process. The inductances of various line inductors implemented with printed circuit boards were measured. The feasibility of the proposed line inductor was successfully demonstrated.

• 한국전자파학회논문지
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• 제12권7호
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• pp.1048-1056
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• 2001

고속 다층 인쇄 회로 기판의 전원 평면과 접지 평면을 통해 전파되는 SSN 잡음의 영향을 감소시키기 위하여 일반적으로 디커플링 캐패시터를 사용한다. 본 논문에서는 디커플링 캐패시터에 대한 간단한 고주파 측정 방법 을 제시하고 고주파 기생 성분들을 고려한 광대역 (50 MHz ~3 GHz) 등가 회로 모델을 제안하였다. 제안된 모델은 SSN의 영향을 분석하기 위한 전원 평면과 접지 평면의 SPICE 모델과 쉽게 결합할 수 있다. 제안된 모델이 연결된 회로 해석 결과는 측정 결과와 잘 일치하며, 제안된 모델을 이용한 회로 해석을 통해 디커플링 캐패시터 값에 따른 잡음 감소 효과를 빠르고 정확하게 분석할 수 있음을 확인하였다.

• 융복합기술연구소 논문집
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• 제1권1호
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• pp.34-40
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• 2011

In this paper, a hybrid design tool combining one-dimensional(1D) lumped model and three-dimensional computational fluid dynamics(CFD) approach has been developed in order to evaluate the performance of inkjet print head and droplet control process are studied to reduce the deviations between nozzles which affect the size of the printed line for the industrial application of direct writing on printed circuit boards(PCB). 1D lumped model analysis shows that it is useful tool for evaluating performance of an inkjet head by varying the design parameters. The differences in ejected volume and droplet velocity between analytical and experimental result are within 12%. Time sequence of droplet generation is verified by the comparison between 3D analysis result and photographic images acquired by stroboscopic technique. In addition, by applying DPN process, velocity and volume uniformity between nozzles is dramatically improved that the tolerance achieved by the piezoelectric inkjet printhead across the 64 nozzles is 5 to 8%. A printed line pattern is successfully obtained using the fabricated inkjet print head and droplet calibration system.

• 한국정밀공학회지
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• 제27권10호
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• pp.14-22
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• 2010

The most costly and time-consuming process in the fabrication of today's multi-layer circuit board is drilling interconnection holes between adjacent layers and via holes within a layer. Decreasing size of via holes being demanded and growing number of via holes per panel increase drilling costs. Component density and electronic functionality of today's multi-layer circuit boards can be improved with the introduction of cost-effective, variable depth laser drilled blind micro via holes, and interconnection holes. Laser technology is being quickly adopted into the circuit board industry but can be accelerated with the introduction of a true production laser drilling system. In order to get optimized condition for drilling to FPCB (Flexible Printed Circuit Board), we use various drill pattern as drill step. For productivity, we investigate drill path optimization method. And for the precise drilling the thermal drift of scanner and temperature change of scan system are tested.

• 자원리싸이클링
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• 제25권1호
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• pp.24-30
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• 2016

노트북 실장인쇄회로기판(Printed Circuit Board Assembly, PCBA)으로부터 탄탈럼을 회수하기 위한 선별실험을 실시하였다. 우선 노트북 실장인쇄회로기판에 실장된 전자부품(Electronic Components, ECs)을 자체개발한 실험장치를 이용하여 기판으로부터 분리하였다. 분리된 전자부품을 체분리하여 -6.35+2.80 mm구간에서 전체 탄탈럼 캐퍼시터의 약 93.2 wt.%를 회수할 수 있었다. 회수된 탄탈럼 캐퍼시터를 해머밀로 분쇄 후, 자력선별기를 통해 자력세기 300 가우스에서 분쇄물 중의 전극을 제거하였다. 전극이 제거된 자력선별 산물을 대상으로 넬슨 선별기(Knelson concentrator)를 이용한 선별 실험 결과 Bowl의 회전수 200 rpm, 유동층수 유량 7 L/min에서 76.9%의 최대 선별효율을 보였으며, 이때 품위 및 회수율은 각각 약 81.1%, 약 78.8%를 나타내었다.

• 반도체디스플레이기술학회지
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• 제10권4호
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• pp.125-130
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• 2011

The recent PCB (Printed Circuit Board) wet etcher has been needed to process pattern within $20{\mu}m$ width on a $20{\mu}m$ thick board. A previous PCB etcher can be used with multiple points of roller rolls or slips off a board. Also, the damage of the board by contacting the roller increases the friction defects. A vertical type boards transporting process is developed to solve the problems of boards friction and sagging in a horizontal etcher. In this research, CFD (Computational Fluid Dynamics) method is used to design an improved spray nozzle including the critical part of etcher, and establish the design method. Meanwhile, major spray characteristics are expected in diverse nozzle types and variables. Lastly, diverse simulation results are adapted to design an improved nozzle and spray system.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2001년도 추계학술발표회 초록집
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• pp.3-3
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• 2001

Two companies plating baths were selected for plating on phenol and epoxy resin boards as well as on flexible p polyimide boards. After plating, deposited i&IIk&.ness al1d physical properties, as well as solder wettabilities by aging with $150^{\circ}C$ heating and 100% humidity were compared. After plating and aged with two different tin baths, deposited thickness and physical properties were not so great differences, but solder wettabilities were superior used polymer catalyst than the other. Furthermore depend upon the compactness and fineness of metallic sturctures of the base copper, the amounts of the plated copper were big differel1lces. These differences seems to be inherited from the kind and amount of additives. as well as current densities, which are influences upon structures of Copper layers. Generally the tin thickness are hetween 0.5 to $1.0\mu\textrm{m}$ and thicker the solder wettabilities are the better, and also me compact structures of deposits showed gooo soidierabiiities. In this study, with our own deveiotaedl plating equipment could get more than $0.5\mu\textrm{m}$ of till thickness and piating speed was $0.1\mu\textrm{m}$ per minutes.

• 대한기계학회논문집
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• 제13권4호
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• pp.771-779
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• 1989

본 연구에서는 기판의 양면에 부품이 SMT방법으로 탑재되어 있는 경우에 기판사이에 형성되는 유동채널에서의 열전달 및 유동특성을 연구하였다.

• Industrial Engineering and Management Systems
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• 제12권4호
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• pp.330-335
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• 2013

A surface mount device (SMD) assembles electronic components on printed circuit boards (PCB). Since a component assembly process is a bottleneck process in a PCB assembly line, making an efficient SMD plan is critical in increasing the PCB assembly line productivity. Feeder assignment is an important part of the SMD plan optimization. In this paper, we propose a feeder re-assign improvement algorithm for a specific type of SMD machine with a piano type multi-head gantry. Computational results on some real-world benchmark data sets show the effectiveness of our proposed algorithm.