• Proceedings of the KIEE Conference
• /
• 1998.07c
• /
• pp.1125-1127
• /
• 1998

Inchon International Airport(IIA) is constructed for Northeast Asia Gate as is important for IIA to become a 21 century's leader in the world. as is planned for open at December 2000 as a important economic link for unified korea. Power System is designed through investigation of advanced domestic and international example. In addition to power facility operation it is designed for using an information infrastructure of whole airport. IIA Power System Design make instantaneously the Power Distribution Facilities and the SCADA System to construct the airport. and the Airport Power Information System to operate the Power System. It is designed to take efficient and safe Power System including the advanced technology. Power System make the integrated Power Information Database to operate the Main Control Center, analyze the data about the relation of the Power System and Airport operation, and will support the important files in the future.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.4 no.4
• /
• pp.307-311
• /
• 2004

This paper presents an efficient architecture that optimizes the design of SEED S-box using composite field arithmetic. SEED is the Korean standard 128-bit block cipher algorithm developed by Korea Information Security Agency. The nonlinear function S-box is the most costly operation in terms. of size and power consumption, taking up more than 30% of the entire SEED circuit. Therefore the S-box design can become a crucial factor when implemented in systems where resources are limited such as smart cards. In this paper, we transform elements in $GF(2^8)$ to composite field $GF(((2^2)^2)^2)$ where more efficient computations can be implemented and transform the computed result back to $GF(2^8)$. This technique reduces the S-box portion to 15% and the entire SEED algorithm can be implemented at 8,700 gates using Samsung smart card CMOS technology.

• Transactions of the Korean Society of Automotive Engineers
• /
• v.2 no.5
• /
• pp.110-120
• /
• 1994

Due to the increasing demands in comfortable drivability, most motor companies are developing their own unique shift controller to suppress the shift shock induced by gear change. For a typical automatic transmission system, the dynamic constraints of friction clutch was clarified for efficient program development and major factors effecting the shift transient was confirmed by simulation study. The MIMO LQG/LTR controller was designed to control the turbine and corresponding gear speed. By establishing the control strategy recalling transient response during shift the speed controller mentioned above was used as an indirect torque controller. Consequently a new concept for a systematic design method of shift controller applicable to wide-varying systems was suggested which is time efficient and cost efficient saving a lot of experimental study.

• Journal of Power System Engineering
• /
• v.15 no.5
• /
• pp.72-76
• /
• 2011

In this work, the parameter optimization for thermal-sprayed Al/SiC composites have been designed by $L_9(3^4)$ orthogonal array and analysis of variance(ANOVA). Al/SiC composites were fabricated by flame spray process on steel substrate. The hardness of composites were measured using micro-vickers hardness tester, and these results were analyzed by ANOVA. The ANOVA results showed that the oxygen gas flow, powder feed rate and spray distance affect on the hardness of the Al/SiC composites. From the ANOVA results, the optimal combination of the flame spray parameters could be extracted. It was considered that experimental design using orthogonal array and ANOVA was efficient to determine optimal parameter of thermal-sprayed Al/SiC composites.

• ETRI Journal
• /
• v.25 no.6
• /
• pp.510-516
• /
• 2003

In this paper, we describe the development of a platform-based SoC of a 32-bit smart card. The smart card uses a 32-bit microprocessor for high performance and two cryptographic processors for high security. It supports both contact and contactless interfaces, which comply with ISO/IEC 7816 and 14496 Type B. It has a Java Card OS to support multiple applications. We modeled smart card readers with a foreign language interface for efficient verification of the smart card SoC. The SoC was implemented using 0.25 ${\mu}m$ technology. To reduce the power consumption of the smart card SoC, we applied power optimization techniques, including clock gating. Experimental results show that the power consumption of the RSA and ECC cryptographic processors can be reduced by 32% and 62%, respectively, without increasing the area.

• Proceedings of the Korea Society of Information Technology Applications Conference
• /
• 2005.11a
• /
• pp.81-84
• /
• 2005

Various design schemes for network using wireless sensor nodes have been widely studied on the several application areas ranging from the real world information collection to environmental monitor. Currently, the schemes are focused on the design of sensor network for low power consumption, power-aware routing protocol, micro miniature operating system and sensor network middleware. The indoor localization system that identifies the location of the distributed nodes in a wireless sensor network requires features dealing with mobility, plurality and other environmental constraints of a sensor node. In this paper, we present an efficient location system to cope with mobility of multiple mobile nodes by designing a location handler that processes location information selectively depending on the nodes' density in a specific region. In order to resolve plurality of multiple mobile nodes, a routing method for the location system is also proposed to avoid the occurrence of overlapped location data.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.3
• /
• pp.42-47
• /
• 2011

The partial product matrix (PPM) of a parallel squarer is symmetric. To reduce the depth of PPM, it can be folded, shifted and rearranged. In this paper, we present an area-efficient squarer design method using new partial product rearrangement. Also, a fixed-width squarer design method of the proposed squarer is presented. By simulations, it is shown that the proposed squarers lead to up to 17% reduction in area, 10% reduction in propagation delay and 10% reduction in power consumption compared with previous squarers. By using the proposed fixed-width squarers, the area, propagation delay and power consumption can be further reduced up to 30%, 16% and 28%, respectively.

• Journal of Digital Contents Society
• /
• v.14 no.4
• /
• pp.529-536
• /
• 2013

Lack of proper amount of sun lights and wind strength which are major factors of solar power and wind power system may cause poor electric power generation and decrease the lifetime of batteries that are major energy saving units. Because the PCS, which is essential in solar and wind power system, for small power generation system has been rarely developed an efficient and stable PCS for small power generation system is highly required. In this paper, we design a new constant current/constant voltage type hybrid PCS by which stand alone/grid connected operation with commercial power system is available and implement the designed PCS as a protype for performance verification.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.06a
• /
• pp.115-115
• /
• 2009

Current sensing in power semiconductors involves sensing of over-current in order to protect the device from harsh conditions. This technique is one of the most important functions in stabilizing power semiconductor device modules. The Power MOSFET is very efficient method with low power consumption, fast sensing speed and accuracy. In this paper, we have analyzed the characteristics of proposed sense FET and optimized its electrical characteristics to apply conventional 40 V power MOSFET by numerical and simulation analysis. The proposed sense FET has the n-drift doping concentration $1.5\times10^{14}\;cm^{-3}$, size of $600\;{\mu}m^2$ with $4.5\;{\Omega}$, and off-state leakage current below $50\;{\mu}A$. We offer the layout of the proposed Power MOSFET to process actually. The offerd design and optimization methods are meaningful, which the methods can be applied to the power devices having various breakdown voltages for protection.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.15 no.4
• /
• pp.259-265
• /
• 2010

The proposed method offers an improved control method for high power density AC/DC adapter by using more energy efficient electrical equipments. Power factor corrector (PFC) topology is based on boost topology with boundary conduction mode (BCM) and DC/DC topology is based on LLC resonant converter, which helps to reduce size of the semiconductor and the magnetic devices. Test results with 85W AC/DC adapter (18.5V/4.6A) design shows that the measured efficiency is 90% at $90V_{rms}$ input voltage with power density of $36W/in^3$. It also shows low no load power consumption of about 0.5W.