• Journal of information and communication convergence engineering
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• v.10 no.1
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• pp.85-90
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• 2012

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

• Journal of Electrical Engineering and Technology
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• v.10 no.1
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• pp.195-204
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• 2015

In this paper, the development of a cost-effective active power filter/uninterruptible power supply (APF/UPS) system with seamless mode transfer is described. The proposed scheme employs a pulse-width-modulation (PWM) voltage-source inverter and has two operational modes. First, when the source voltage is normal, the system operates as an APF, which compensates for the harmonics and power factor while boosting the DC-link voltage to be ready for the disturbance, without an additional DC charging circuit. A simple algorithm to detect the load current harmonics is also proposed. Second, when the source voltage is out of the normal range (owing to sag, swell, or outage), it operates a UPS, which controls the output voltage constantly by discharging the DC-link capacitor. Furthermore, a seamless transfer method for the single-phase inverter between the APF mode and the UPS mode is also proposed, in which an IGBT switch with diodes is used as a static bypass switch. Dissimilar to a conventional SCR switch, the IGBT switch can implement a seamless mode transfer. During the UPS operation, when the source voltage returns to the normal range, the system operates as an APF. The proposed system has good transient and steady-state response characteristics. The APF, charging circuit, and UPS systems are implemented in one inverter system. Finally, the validity of the proposed scheme is investigated with simulated and experimental results for a prototype APF/UPS system rated at 3 kVA.

• Journal of Power Electronics
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• v.14 no.1
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• pp.48-60
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• 2014

Multilevel inverters have been widely used for high-voltage and high-power applications. Their performance is greatly superior to that of conventional two-level inverters due to their reduced total harmonic distortion (THD), lower switch ratings, lower electromagnetic interference, and higher dc link voltages. However, they have some disadvantages such as an increased number of components, a complex pulse width modulation control method, and a voltage-balancing problem. In this paper, a novel nine-level reduced switch cascaded multilevel inverter based on a multilevel DC link (MLDCL) inverter topology with reduced switching components is proposed to improve the multilevel inverter performance by compensating the above mentioned disadvantages. This topology requires fewer components when compared to diode clamped, flying capacitor and cascaded inverters and it requires fewer carrier signals and gate drives. Therefore, the overall cost and circuit complexity are greatly reduced. This paper presents modulation methods by a novel reference and multicarrier based PWM schemes for reduced switch cascaded multilevel inverters (RSCMLI). It also compares the performance of the proposed scheme with that of conventional cascaded multilevel inverters (CCMLI). Simulation results from MATLAB/SIMULINK are presented to verify the performance of the nine-level RSCMLI. Finally, a prototype of the nine-level RSCMLI topology is built and tested to show the performance of the inverter through experimental results.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.8
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• pp.5201-5206
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• 2014

A 'Light switch remote control' was made with an android smartphone and a smart light switch, which can use wireless communication on this paper. A smart light switch uses an embedded board and Bluetooth communication to receive and transmit data, and it receives and sends data again with a smartphone and wireless communication. This study used the flexibility of sensors that could be added later to utilize the embedded board as a gateway. This skill is being serviced now in a new apartment and building. On the other hand, existing households that do not support this skill can use it if they change only the switch. In conclusion, this system ensured user convenience and flexibility of system.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.4
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• pp.375-387
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• 2015

This study investigates an economic and highly efficient power-converter topology and its modulation scheme for 60 kW rapid EV charger system. The target system is a three-phase three-switch buck-type rectifier topology. A new carrier-based PWM scheme, which is characterized by simple implementation using logic gates, is introduced in this paper. This PWM scheme replaces the diode rectifier equivalent switching state with an active switching state to produce the same effective current flowing path. As a result, the distortion of input current during the polarity reversal of capacitor line voltage can be mitigated. The proposed modulation technique is confirmed through simulation verification. The proposed modulation technique and its implementation scheme can expand the operation range of the three-phase three-switch buck-type rectifier with high-quality AC input and capacitor ripple current.

• Journal of the Korea Society of Computer and Information
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• v.22 no.6
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• pp.123-129
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• 2017

In this paper, we proposed a smart multiple-tap system which a remote user with smartphone can control multiple-taps in order to reduce standby-power consumption more conveniently when plugged-in electric appliances are turned-off. Recently, several researches of smart multiple-tap using IoT technology has reported. However, in these researches, an additional device like as a server computer is necessary, or multiple-taps could be only remotely controlled by smartphone and not directly controlled by on/off switch. The proposed smart multiple-tap system does not need any additional device only if it has a WiFi router, and it can be used for user as well as remote control using smartphone application and physically direct control using contact switches like existing multiple-taps. Our approach is to develop a smart multiple-tap device capable of WiFi communication can each serve as a server or a client, and can be operated by the hybrid switch combining the on/off contact switch and the relay switch. We implemented the prototype of the proposed system composed of the smart multiple-tap device and the smartphone application, and the test of the prototype validates the proposed system.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.3
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• pp.161-168
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• 2019

This study introduces a new topology to decrease the voltage stress experienced by a 13.56 MHz electrical variable capacitor (EVC) circuit with an asymmetrical switch structure applied to the impedance matching circuit of a radio frequency (RF) plasma system. The method adopts a symmetrical switch structure instead of an asymmetrical one in each of the capacitor's leg in the EVC circuit. The proposed topology successfully reduces voltage stress in the EVC circuit due to the symmetrical charging and discharging mode. This topology can also be applied to the impedance matching circuit of a high-power and high-frequency RF etching system. The target features of the proposed circuit topology are investigated via simulation and experiment. Voltage stress on the switch of the EVC circuit is successfully reduced by more than 40%.

• The Journal of the Acoustical Society of Korea
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• v.38 no.2
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• pp.222-230
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• 2019

In this paper, the power of the energy harvesting circuit using the PVDF (Polyvinylidene fluoride) piezoelectric sensor transformed by vortex was analyzed. For power analysis, a general bridge diode rectifier circuit and a P-SSHI (Parallel Synchronized Switch Harvesting on Inductor) rectifier circuit with a switching circuit were used. The P-SSHI circuit is a circuit that incorporates a parallel synchronous switch circuit at the input of a general rectifier circuit to improve energy conversion efficiency. In this paper, the output power of general rectifier circuit and P-SSHI rectifier circuit is analyzed and verified through theory and experiment. It was confirmed that the efficiency was increased by 69 % through the experiment using the wind. In addition, a circuit for storing the harvested energy in the supercapacitor was implemented to confirm its applicability as a secondary battery.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.6
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• pp.404-410
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• 2021

This paper proposes a high step-up converter with zero-voltage transition (ZVT) cell for fuel cell electric vehicle. The proposed converter applies a ZVT cell to a dual floating output boost converter (DFOBC) so that not only the main switch but also the ZVT switch can achieve full-range soft switching. The current rating of the ZVT switch is 17% of the main switch. The proposed converter has high reliability in that no timing issue occurs. Therefore, online calculation is not required. The minimum turn-on time of the ZVT switch that guarantees soft switching at all loads and input/output voltage is obtained by analysis. In addition, the proposed DFOBC allows the use of a 650 V device even at 800 V output and has the advantage of being able to boost the voltage by 3.5 times with 0.56 duty. Planar coupled inductor with PCB winding was successfully implemented with the converter operated at 300 kHz. The 25 kW prototype achieves peak efficiency of 99% and power density of 63 kW/L.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.5
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• pp.35-41
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• 2008

This paper presents the design method of current-mode signal processing for high speed and low power digital audio signal processing. The digital audio processor requires a digital signal processing such as fast Fourier transform (FFT), which has a problem of large power consumption according to the settled point number and high speed operation. Therefore, a current-mode signal processing with a switched Current (SI) circuit was employed to the digital audio signal processing because a limited battery life should be considered for a low power operation. However, current memory that construct a SI circuit has a problem called clock-feedthrough. In this paper, we examine the connection of dummy MOS that is the common solution of clock-feedthrough and are willing to calculate the relation of width between dummy MOS for a proposal of the design methodology for improvement of current memory. As a result of simulation, in case of that the width of memory MOS is 20um, ratio of input current and bias current is 0.3, the relation of width between switch MOS and dummy MOS is $W_{M4}=1.95W_{M3}+1.2$ for the width of switch MOS is 2~5um, it is $W_{M4}=0.92W_{M3}+6.3$ for the width of switch MOS is 5~10um. Then the defined relation of MOS transistors can be a useful design guidance for a high speed low power digital audio processor.