• International Journal of Computer Science & Network Security
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• v.22 no.12
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• pp.37-50
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• 2022

Modern supply chains include multiple activities from collecting raw materials to transferring final products. These activities involve many parties who share a huge amount of valuable data, which makes managing supply chain systems a challenging task. Current supply chain management (SCM) systems adopt digital technologies such as the Internet of Things (IoT) and blockchain for optimization purposes. Although these technologies can significantly enhance SCM systems, they have their own limitations that directly affect SCM systems. Security, performance, and scalability are essential components of SCM systems. Yet, confidentiality and scalability are one of blockchain's main limitations. Moreover, IoT devices are lightweight and have limited power and storage. These limitations should be considered when developing blockchain-based IoT-SCM systems. In this paper, the requirements of efficient supply chain systems are analyzed and the role of both IoT and blockchain technologies in providing each requirement are discussed. The limitations of blockchain and the challenges of IoT integration are investigated. The limitations of current literature in the same field are identified, and a secure and scalable blockchain-based IoT-SCM system is proposed. The proposed solution employs a Hyperledger fabric blockchain platform and tackles confidentiality by implementing private data collection to achieve confidentiality without decreasing performance. Moreover, the proposed framework integrates IoT data to stream live data without consuming its limited resources and implements a dualstorge model to support supply chain scalability. The proposed framework is evaluated in terms of security, throughput, and latency. The results demonstrate that the proposed framework maintains confidentiality, integrity, and availability of on-chain and off-chain supply chain data. It achieved better performance through 31.2% and 18% increases in read operation throughput and write operation throughput, respectively. Furthermore, it decreased the write operation latency by 83.3%.

• KIISE Transactions on Computing Practices
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• v.20 no.11
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• pp.604-609
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• 2014

Decoding processes in portable media players have a high computational cost, resulting in high power consumption by the CPU. If decoding computations are reduced, the power consumed by the CPU is also be reduced, but such a choice generally results in a degradation of the video quality for the users, so it is essential to address this tradeoff. We proposed a new CPU power management scheme that can make use of the scalability property available in the H.164/SVC standard. We first proposed a new video quality model that makes use of a video quality metric(VQM) in order to efficiently take into account the different quantization factors in the SVC. We then propose a new dynamic voltage scaling(DVS) scheme that can selectively combine the previous decoding times and frame sizes in order to accurately predict the next decoding time. We then implemented a scheme on a commercial smartphone and performed a user test in order to examine how users react to the VQM difference. Real measurements show that the proposed scheme uses up to 34% fewer energy than the Linux DVFS governor, and user tests confirm that the degradation in the quality is quite tolerable.

• Journal of information and communication convergence engineering
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• v.10 no.4
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• pp.405-410
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• 2012

Several attempts have been made to add journaling capability to a traditional file allocation table (FAT) file system. However, they encountered issues such as excessive system load or instability of the journaling data itself. If journaling data is saved as a file format, it can be corrupted by a user application. However, if journaling data is saved in a fixed area such as a reserved area, the storage can be physically corrupted because of excessive system load. To solve this problem, a new method that dynamically allocates journaling data is introduced. In this method, the journaling data is not saved as a file format. Using a reserved area and reserved FAT status entry of the FAT file system specification, the journaling data can be dynamically allocated and cannot be accessed by user applications. The experimental results show that this method is more stable and scalable than other log-based FAT file systems. HFAT was tested with more than 12,000 power failures and was stable.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.98-103
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• 2008

1T1C DRAM has been facing technological and physical constraints that make more difficult their further scaling. Thus there are much industrial interests for alternative technologies that exploit new devices and concepts to go beyond the 1T1C DRAM technology, to allow better scaling, and to enlarge the memory performance. The technologies of DRAM cell are changing from 1T1C cell type to capacitor-less 1T-gain cell type for more scalable cell size. But floating body cell (FBC) of 1T-gain DRAM has weak retention properties than 1T1C DRAM. FET-type 1T-FeRAM is not adequate for long term nonvolatile applications, but could be a good alternative for the short term retention applications of DRAM. The proposed nonvolatile refresh scheme is based on utilizing the short nonvolatile retention properties of 1T-FeRAM in both after power-off and power-on operation condition.

• Journal of Korea Society of Industrial Information Systems
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• v.24 no.1
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• pp.31-38
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• 2019

In this paper, we develop a beamforming front end platform with pipeline circuit configuration method that can apply various clinical diagnostic applications of ultrasound image technology. Hardware design targets compression applications as well as scalable applications where power, integration levels and replication possibilities are important. Firmware design was implemented to achieve optimal FPGA parallel processing level by constructing new IP and system-oriented design environment to accelerate design productivity with maximum productivity improvement using Vivado HLS tool, which is a next generation high level synthesis tool. Former supports the high-speed management function of scan data that can create an image area arbitrarily and can be appropriately corrected and supplemented when reconfiguring or changing system specifications in the future.

• ETRI Journal
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• v.31 no.5
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• pp.510-517
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• 2009

A high throughput parallel decoding method is developed for context-based adaptive variable length codes. In this paper, several new design ideas are devised and implemented for scalable parallel processing, a reduction in area, and a reduction in power requirements. First, simplified logical operations instead of memory lookups are used for parallel processing. Second, the codes are grouped based on their lengths for efficient logical operation. Third, up to M bits of the input stream can be analyzed simultaneously. For comparison, we designed a logical-operation-based parallel decoder for M=8 and a conventional parallel decoder. High-speed parallel decoding becomes possible with our method. In addition, for similar decoding rates (1.57 codes/cycle for M=8), our new approach uses 46% less chip area than the conventional method.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.139-142
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• 2003

Location information of individual nodes is useful for routing and some other functions in wireless sensor networks. Each node can use GPS to know its position. However, the GPS service can not be practical to use due to cost efficiency, power, and computing capability. This paper proposes the localization method to make nodes know their location in case of a few nodes knows their position information. The proposed method is named as VALT (Virtual Anchor based Localization using Triangulation method). It uses the virtual anchor concept and calculates the location of individual nodes by means of the triangulation method. This method helps all nodes to determine their position with low cost and high scalability.

• Journal of Electrical Engineering and Technology
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• v.6 no.4
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• pp.573-579
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• 2011

To meet the scalability and performance requirements of data analyses, which often involve voluminous data, efficient parallel or concurrent algorithms and frameworks are essential. We present a high-performance Korean morphological analyzer which employs the MapReduce framework on the graphics processing unit (GPU). MapReduce is a programming framework introduced by Google to aid the development of web search applications on a large number of central processing units (CPUs). GPUs are designed as a special-purpose co-processor. Their programming interfaces are typically formulated for graphics applications. Compared to CPUs, GPUs have greater computation power and memory bandwidth; however, GPUs are more difficult to program because of the design of their architectures. The performance of the Korean morphological analyzer using the MapReduce framework on the GPU is evaluated in comparison with the CPU-based model. The proposed Korean Morphological analyzer shows promising scalable performance on distributed computing with the GPU.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.26 no.7
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• pp.23-29
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• 2012

A single line diagram is a graphic user interface to represent electrical connectivity between power equipments in distribution automation systems. This paper proposes a new single line auto-drawing technique based on the service oriented architecture. Web service, CIM(Common Information Model) and SVG(Scalable Vector Graphics) are adopted to implement SOA concept. A web service demo system was established which is configured with the service provider, consumer and broker to verify the feasibility of this study.

• Journal of Communications and Networks
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• v.5 no.3
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• pp.202-214
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• 2003

The central challenge in the design of ad-hoc networks is the development of dynamic routing protocol that efficiently finds route between mobile nodes. Several routing protocols such as DSR, AODV and DSDV have been proposed in the literature to facilitate communication in such dynamically changing network topology. In this paper, a Node Transition Probability (NTP) based routing algorithm, which determines stable routes using the received power from all other neighboring nodes is proposed. NTP based routing algorithm is designed and implemented using Global Mobile Simulator (GloMoSim), a scalable network simulator. The performance of this routing algorithm is studied for various mobility models and throughput, control overhead, average end-to-end delay, and percentage of packet dropped are compared with the existing routing protocols. This algorithm shows acceptable performance under all mobility conditions. The results show that this algorithm maximizes the bandwidth utilization during heavy traffic with lesser overhead.