• Title/Summary/Keyword: power scalable

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STO-based Cluster Header Election Algorithm (STO 기반 클러스터 헤더 선출 알고리즘)

  • Yoon, Jeong-Hyeon;Lee, Heon-Guk;Kim, Seung-Ku
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2019.05a
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    • pp.587-590
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    • 2019
  • This paper is about to improve the network life's reduction due to the deviation of sensor node and frequently change of network, the main problem of sensor network. The existing Scalable Topology Organization(STO)-based ZigBee Tree Topology Control Algorithm did not consider ways to consume power so the network lifetime is too short. Accordingly, per each round, electing a new parent node and consisting of the new network topology technique, The Cluster Header Selection, extending the network's overall lifetime. The OMNet++ Simulator yielded results from the existing STO Algorithm and the proposed Cluster Header Selection Technique in the same experimental environment, which resulted in an increase in overall network life by about 40% and an improvement of about 10% in performance in the remaining portion of the battery.

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Dual Coalescent Energy-Efficient Algorithm for Wireless Mesh Networks

  • Que, Ma. Victoria;Hwang, Won-Joo
    • Journal of Korea Multimedia Society
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    • v.10 no.6
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    • pp.760-769
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    • 2007
  • In this paper, we consider a group mobility model to formulate a clustering mechanism called Dual Coalescent Energy-Efficient Algorithm (DCEE) which is scalable, distributed and energy-efficient for wireless mesh network. The differences of the network nodes will be distinguished to exploit heterogeneity of the network. Furthermore, a topology control, that is, adjusting the transmission range to further reduce power consumption will be integrated with the cluster formation to improve network lifetime and connectivity. Along with network lifetime and power consumption, clusterhead changes will be measured as a performance metric to evaluate the. effectiveness and robustness of the algorithm.

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A Novel Control Technique for a Multi-Output Switched-Resonant Converter

  • Sundararaman, K.;Gopalakrishnan, M.
    • Journal of Power Electronics
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    • v.13 no.6
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    • pp.928-938
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    • 2013
  • This paper proposes a novel control method for a multi-output switched-resonant converter. Output voltage can be regulated against variations in the supply voltage and load by controlling the voltage of the resonant capacitor (pulse amplitude control). Precise control is possible when pulse amplitude control is combined with pulse number control. The converter is analyzed, and design considerations are explained by using examples. Control implementation is described and load regulation and ripples are analyzed by simulation and hardware results. The topology is modified to obtain an additional negative output without any additional hardware other than a diode. The analysis of such a triple output converter with two positive outputs and one negative output is conducted and confirmed. The topology and control scheme are scalable to any number of outputs.

Multi-Valued Logic Device Technology; Overview, Status, and Its Future for Peta-Scale Information Density

  • Kim, Kyung Rok;Jeong, Jae Won;Choi, Young-Eun;Kim, Woo-Seok;Chang, Jiwon
    • Journal of Semiconductor Engineering
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    • v.1 no.1
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    • pp.57-63
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    • 2020
  • Complementary metal-oxide-semiconductor (CMOS) technology is now facing a power scaling limit to increase integration density. Since 1970s, multi-valued logic (MVL) has been considered as promising alternative to resolve power scaling challenge for increasing information density up to peta-scale level by reducing the system complexity. Over the past several decades, however, a power-scalable and mass-producible MVL technology has been absent so that MVL circuit and system implementation have been delayed. Recently, compact MVL device researches incorporating multiple-switching characteristics in a single device such as 2D heterojunction-based negative-differential resistance (NDR)/transconductance (NDT) devices and quantum-dot/superlattices-based constant intermediate current have been actively performed. Meanwhile, wafer-scale, energy-efficient and variation-tolerant ternary-CMOS (T-CMOS) technology has been demonstrated through commercial foundry. In this review paper, an overview for MVL development history including recent studies will be presented. Then, the status and its future research direction of MVL technology will be discussed focusing on the T-CMOS technology for peta-scale information processing in semiconductor chip.

Flexible Thermoelectric Device Using Thick Films for Energy Harvesting from the Human Body

  • Cho, Han Ki;Kim, Da Hye;Sin, Hye Sun;Cho, Churl-Hee;Han, Seungwoo
    • Journal of the Korean Ceramic Society
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    • v.54 no.6
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    • pp.518-524
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    • 2017
  • A flexible thermoelectric device using body heat has drawn attention as a power source for wearable devices. In this study, thermoelectric thick films were fabricated by cold pressing method using p-type antimony telluride and n-type bismuth telluride powders in accordance with specific loads. Thermoelectric thick films were denser and improved the electrical and thermoelectric properties while increasing the load of the cold pressing. The thickness of the specimen can be controlled by the amount of material; specimens were approximately 700 um in thickness. Flexible thermoelectric devices were manufactured by using the thermoelectric thick films on PI (Polyimide) substrate. The process is cheap, efficient, easy and scalable. Evaluation of power generation performance and flexibility on the fabricated flexible thermoelectric device was carried out. The flexible thermoelectric device has great flexibility and good performance and can be applied to wearable electronics as a power source.

Inductorless 8.9 mW 25 Gb/s 1:4 DEMUX and 4 mW 13 Gb/s 4:1 MUX in 90 nm CMOS

  • Sekiguchi, Takayuki;Amakawa, Shuhei;Ishihara, Noboru;Masu, Kazuya
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.10 no.3
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    • pp.176- 184
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    • 2010
  • A low-power inductorless 1:4 DEMUX and a 4:1 MUX for a 90 nm CMOS are presented. The DEMUX can be operated at a speed of 25 Gb/s with the power supply voltage of 1.05 V, and the power consumption is 8.9 mW. The area of the DEMUX core is $29\;{\times}\;40\;{\mu}m^2$. The operation speed of the 4:1 MUX is 13 Gb/s at a power supply voltage of 1.2 V, and the power consumption is 4 mW. The area of the MUX core is $30\;{\times}\;18\;{\mu}m^2$. The MUX/DEMUX mainly consists of differential pseudo-NMOS. In these MUX/DEMUX circuits, logic swing is nearly rail-to-rail, and a low $V_{dd}$. The component circuit is more scalable than a CML circuit, which is commonly used in a high-performance MUX/DEMUX. These MUX/DEMUX circuits are compatible with conventional CMOS logic circuit, and it can be directly connected to CMOS logic gates without logic level conversion. Furthermore, the circuits are useful for core-to-core interconnection in the system LSI or chip-to-chip communication within a multi-chip module, because of its low power, small footprint, and reasonable operation speed.

OCP Cold Storage Test-bed (OCP Cold Storage 테스트베드)

  • Lee, Jaemyoun;Kang, Kyungtae
    • KIISE Transactions on Computing Practices
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    • v.22 no.3
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    • pp.151-156
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    • 2016
  • Cloud computing systems require a huge number of storage servers due to the growing implications of power bills, carbon emissions, and logistics of data centers. These considerations have motivated researchers to improve the energy efficiency of storage servers. Most servers use a lot of power irrespective of the amount of computing that they are doing, and one important goal is to redesign servers to be power-proportional. However, Research on large-scale storage systems is hampered by their cost. It is therefore desirable to develop a scalable test-bed for evaluating the power consumption of large-scale storage systems. We are building on open-source projects to construct a test-bed which will contribute to the assessment of power consumption in tiered storage systems. Integrating the cloud application platform can easily extend the proposed testbed laying a foundation for the design and evaluation of low-power storage servers.

Fast Intermode Decision for Scalable Video Coding using Statistical Hypothesis Testing (스케일러블 비디오 부호화에서 통계적 가설 검증 기법을 이용한 고속 화면간 모드 결정)

  • Lee, Bum-Shik;Hahm, Sang-Jin;Kim, Byung-Sun;Lee, Keun-Sik;Park, Keun-Soo;Kim, Mun-Churl
    • Journal of Broadcast Engineering
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    • v.12 no.3
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    • pp.250-265
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    • 2007
  • In this paper, a fast intermode decision scheme is introduced by efficiently performing the mode decision using statistical hypothesis testing for hierarchical B-picture coding of SVC, in which much computational power is expensed for combined variable block sizes and hierarchical B-pictures. The hypothesis testing in the proposed method is performed on $16{\times}16\;and\;8{\times}8$ blocks to have early termination for RD computation of all possible modes. The early termination in intermode decision is performed by comparing the pixel values of current blocks and corresponding motion-compensated blocks. The proposed scheme exhibits effective early termination behavior in intermode decision and leads to a significant reduction up to 69% in computational complexity with slight increment in bit amounts. The degradation of visual quality turns out to be negligible in terms of PSNR values.

A study on performance evaluation of DVCs with different coding method and feasibility of spatial scalable DVC (분산 동영상 코딩의 코딩 방식에 따른 성능 평가와 공간 계층화 코더로서의 가능성에 대한 연구)

  • Kim, Dae-Yeon;Park, Gwang-Hoon;Kim, Kyu-Heon;Suh, Doug-Young
    • Journal of Broadcast Engineering
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    • v.12 no.6
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    • pp.585-595
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    • 2007
  • Distributed video coding is a new video coding paradigm based on Slepian-Wolf and Wyner-Ziv's information theory Distributed video coding whose decoder exploits side information transfers its computational burden from encoder to decoder, so that encoding with light computational power can be realized. RD performance is superior than that of standard video coding without motion compensation process but still has a gap with that of coding with motion compensation process. This parer introduces basic theory of distributed video coding and its structure and then shows RD performances of DVCs whose coding style is different from each other and of a DVC as a spatial scalable video coder.

A Scalable Hybrid P2P MMOG Cloud Architecture for Load Management in a Region (영역내 부하 관리를 위한 확장적 하이브리드 P2P MMOG 클라우드 구조)

  • Kim, Jin-Hwan
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.22 no.3
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    • pp.83-91
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    • 2022
  • This paper proposes a scalable hybrid P2P(peer-to-peer) cloud architecture for MMOGs(massively multiplayer online games) which includes load management schemes for each region. A game world is divided into several game regions and each game region is serviced by at least one peer(player) in this MMOG cloud environment. The load must be managed regionally to support smooth interactions among them even in the presence of a high concentration of players in a specific region. In the proposed architecture where an efficient and effective provisioning of resources is realized, it is suitable for players to interact with cloud servers effectively and it avoids bottlenecks of the current client-server MMOG architecture. This architecture also relieves a lot of computational power and network traffic, the load on the servers in the cloud by exploiting the capacity of the players. Simulation results show that the proposed hybrid P2P cloud architecture can reduce the considerable bandwidth at the server compared to the client server architecture as the available resources grow with the number of players in crowding or hotspots.