• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.1
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• pp.1-8
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• 2005

In this paper, peak-to-average power ratio (PAPR) of orthogonal frequency division multiplexing (OFDM) with respect to the subchannel coding schemes for interchannel interference (ICI) self-cancellation is analyzed. It is shown theoretically and experimentally that a shaping component is generated in the transmitted sequence in the conventional correlative coding where a pair of antipodal signals is assigned in adjacent subchannels. Due to the shaping component, the signal powers in the mid and edges of a symbol are scaled by different weighting coefficients, resulting in increased PAPR. To overcome this problem a simple adjacent subchannel coding scheme is presented in this paper. In the new scheme, the shaping component caused by partial repetition of signals is eliminated by assigning a pair of signals in which phase difference varies signal-to-signal. As results, the new scheme has 2-3 dB smaller PAPR than the conventional ICI self-cancellation OFDM while maintaining much higher carrier-to-interference ratio than a normal OFDM system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.3
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• pp.231-241
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• 2004

This paper drives the exact expression of bit error rate(BER) performance for groupwise iterative-multipath interference cancellation(GWI-MPIC) algorithm for cancelling multipath interference components in a coherent high-speed downlink packet access(HSDPA) system of W-CDMA downlink and the BER performance is evaluated by numerical analysis. The performance of GWI-MPIC is compared to the successive interference cancellation(SIC) algorithm for multipath components. From numerical results, the optimal average BER performance of weighting factor ${\beta}$$\_$h/ for interference cancellation is obtained at ‘${\beta}$$\_$h/=0.8’ and then this weighting factor is hereafter applied to other performance analysis. Numerical results showed that the average BER performance of GWI-MPIC algorithm is rapidly degraded at multipath L=6, but is revealed the good performance than that of SIC algorithm in terms of increasing the number of multipath. This results also indicated that the average BER performance is greatly degraded due to increasing interference power more than multicode K=8. The average BER performance of the proposed algorithm is superior to the performance of SIC algorithm about 3 ㏈ for processing gain PG=128 at multipath L=2 and Average BER=1.0${\times}$10$\^$-5/. And also, the results produced good performance in case of linear monotonic reduction of multipath fading channel gain than that of constant channel gain variation, because multipath fading channel gain which is arrived later is small.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.11
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• pp.1262-1270
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• 2007

In this paper, we propose a new distortion cancellation mechanism for a balanced power amplifier structure using the carrier cancellation loop of a feedforward and post-distortion technique. The proposed cross post-distortion balanced linear amplifier can reduce nonlinear components as much as the conventional feedforward amplifier through the output dynamic range and broad bandwidth. Also the proposed system provides higher efficiency than the feedforward. The capacities of power amplifier and error power amplifier in the proposed system are analyzed and compared with those of feedforward amplifier. Also the operation mechanisms of the three kind loops are explained. The proposed cross post-distortion balanced linear power amplifier is implemented at the IMT-2000($f_0=2.14\;GHz$) band. With the commercial high power amplifiers of total power of 240 W peak envelope power fer base-station application, the adjacent channel leakage ratio measurement with wideband code division multiple access 4FA signal shows 18.6 dB improvement at an average output power of 40 dBm. The efficiency of fabricated amplifier Improves about 2 % than the conventional feedforward amplifier.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.6 no.10
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• pp.2455-2472
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• 2012

Although underlay spectrum sharing has been shown as a promising technique to promote the spectrum utilization in cognitive radio networks (CRNs), it may suffer bad secondary performance due to the strict power constraints imposed at secondary systems and the interference from primary systems. In this paper, we propose a two-phase based cooperative transmission protocol with the interference cancellation (IC) and best-relay selection to improve the secondary performance in underlay models under stringent power constraints while ensuring the primary quality-of-service (QoS). In the proposed protocol, IC is employed at both the secondary relays and the secondary destination, where the IC-based best-relay selection and cooperative relaying schemes are well developed to reduce the interference from primary systems. The closed-form expression of secondary outage probability is derived for the proposed protocol over Rayleigh fading channels. Simulation results show that, with a guaranteed primary outage probability, the proposed protocol can achieve not only lower secondary outage probability but also higher secondary diversity order than the traditional underlay case.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5A
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• pp.743-750
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• 2000

In this paper, low-power block filtering architecture for digital If down sampler and up sampler is proposed. Software radio technology requires low power and cost effective digital If down and up sampler. Digital If down sampler and up sampler are accompanied with decimation filter and interpolation filter, respectively. In the proposed down sampler architecture, it is shown that the parallel and low-speed processing architecture can be produced by cancellation of inherent up sampler of block filter and down sampler. Proposed up sampler also utilizes cancellation of up sampler and inherent down sampler of block filtering structure. The proposed architecture is compared with the conventional polyphase architecture.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1975-1980
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• 2004

A parallel active power filter is designed and implemented to compensate for undesired current harmonics generated by a nonlinear load. The filter works based on PWM strategy and control signal is generated using a model predictive controller. To evaluate the achievements, a PI controller is also designed and implemented. Experimental results indicate about 50% increase in the efficiency over PI controller.

• Journal of Institute of Control, Robotics and Systems
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• v.9 no.1
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• pp.10-21
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• 2003

During seek operation in disk drives, the recording head is moved toward desired track by seek servo controller and then is settled onto the center of the desired track by settling servo controller. If the head speed at the start of settling servo control is not slow, it may produce overshoot relative to the center of track and thus extend the settling time. The degradation in settling performance will be more severe as the track width becomes smaller for higher density of data storage. We design a new settling servo controller for minimizing settling time based on the pole-zero cancellation. In order to cancel slow poles in settling response, we apply discrete pulse signals to the system in addition to the state feedback control. For exact pole-zero cancellation, we consider the dynamics of power amplifier used for actuator current regulation and the effects of delay in control action. In addition, we present system parameter identification algerian for the robustness of our controller to system parameter variation. In order to demonstrate the practical use of our controller, we present experimental results obtained by using a commercially available disk drive.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.1
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• pp.20-26
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• 2001

Predistorter linearizer having small size and good efficiency is frequently used in High Power Amplifier linearizer system. In this paper, the amount of IMD signal cancellation according to amplitude and phase of predistorter in predistorter type lincarizer is investigated by new experiment method. In the combining method of predistorter type, IMD signal is combined at the amplifier input port, the magnitude and phase of combining signals cannot be easily expected due to different magnitude and phase of incoming signals. By experiment, it is measured that Predistorter linearizer has lower amount of lMD signal cancellation than thoce of Feedforward linearizer at the same condition (amplitude and phase).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.471-473
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• 2009

In this paper, we propose a double talk and noise robust acoustic echo canceler for hands-free telephony applications. The proposed system includes a double-talk detection method that detects the double-talk durations, which uses covariance between microphone input signa and estimated microphone input signal. And proposed adaptive algorithm for estimating acoustic echo path, uses normalized auto-covariance matrix of input signal with multiplication of residual error power and projection order of AP(affine projeciton) algorithm. It is confirmed that the proposed algorithm shows better performance from acoustic interference cancellation (AIC) viewpoint in double talk and noisy environments.

• Journal of Korea Society of Digital Industry and Information Management
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• v.20 no.2
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• pp.63-74
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• 2024

This Paper presents a resistive wideband fully differential low-noise amplifier (LNA) designed using a noise-cancellation technique for TV tuner applications. The front-end of the LNA employs a cascode common-gate (CG) configuration, and cross-coupled local feedback is employed between the CG and common-source (CS) stages. The moderate gain at the source of the cascode transistor in the CS stage is utilized to boost the transconductance of the cascode CG stage. This produces higher gain and lower noise figure (NF) than a conventional LNA with inductor. The NF can be further optimized by adjusting the local open-loop gain, thereby distributing the power consumption among the transistors and resistors. Finally, an optimized DC gain is obtained by designing the output resistive network. The proposed LNA, designed in SK Hynix 180 nm CMOS, exhibits improved linearity with a voltage gain of 10.7 dB, and minimum NF of 1.6-1.9 dB over a signal bandwidth of 40 MHz to 1 GHz.