• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.11
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• pp.1064-1073
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• 2013

In this paper, a compact 370 W high efficiency GaN(Gallium Nitride) HEMT(High Electron Mobility Transistor) power amplifier(PA) using internal harmonic manipulation circuits is presented for cellular and L-band. We employed a new circuit topology for simultaneous high efficiency matching at both fundamental and 2nd harmonic frequency. In order to minimize package size, new 41.8 mm GaN HEMT and two MOS(Metal Oxide Semiconductor) capacitors are internally matched and combined package size $10.16{\times}10.16{\times}1.5Tmm^3$ through package material changes and wire bonded in a new package to improve thermal resistance. When drain biased at 48 V, the developed GaN HEMT power amplifier has achieved over 80 % Drain Efficiency(DE) from 770~870 MHz and 75 % DE at 1,805~1,880 MHz with 370 W peak output power(Psat.). This is the state-of-the-art efficiency and output power of GaN HEMT power amplifier at cellular and L-band to the best of our knowledge.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.9
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• pp.895-902
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• 2014

This paper presents a 2-stage CMOS power amplifier for the 1.75 GHz band using a $0.18-{\mu}m$ CMOS process. Using ADS simulation, a power gain of 28 dB and an efficiency of 45 % at an 1dB compression point of 27 dBm were achieved. The implemented CMOS power amplifier delivered an output power of up to 24.8 dBm with a power-added efficiency of 41.3 % and a power gain of 22.9 dB. For a 16-QAM uplink LTE signal, the PA exhibited a power gain of 22.6 dB and an average output power of 23.1 dBm with a PAE of 35.1 % while meeting an ACLR(Adjacent Channel Leakage Ratio) level of -30 dBc.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.11
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• pp.1220-1228
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• 2010

In this paper, we suggest a scheme to develop an efficient discrete nonlinear model based on polynomial structure for a RF power amplifier(PA). We describe a procedure to extract a discrete nonlinear model such as Taylor series or memory polynomial by sampling the input and output signal of RF PA. The performance of the model is analyzed varying the model parameters such as sample rate, nonlinear order, and memory depth. The results show that the relative error of the model is converged if the parameters are larger than specific values. We suggest an efficient modeling scheme considering complexity of the discrete model depending on the values of the model parameters. Modeling efficiency index(MEI) is defined, and it is used to extract optimum values for the model parameters. The suggested scheme is applied to discrete modeling of various RF PAs with various input signals such as WCDMA, WiBro, etc. The suggested scheme can be applied to the efficient design of digital predistorter for the wideband transmitter.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.6
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• pp.726-732
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• 2019

In this study, we proposed an asymmetric differential inductor to improve the linearity of differential power amplifiers. Considering the phase error between differential signals of the differential amplifier, the location of the center tap of the differential inductor was modified to minimize the error. As a result, the center tap was positioned asymmetrically inside the differential inductor. With the asymmetric differential inductor, the AM-to-AM and AM-to-PM distortions of the amplifier were suppressed. To confirm the feasibility of the inductor, we designed a 2.4 GHz differential CMOS PA for IEEE 802.11n WLAN applications with a 64-quadrature amplitude modulation (QAM), 9.6 dB peak-to-average power ratio (PAPR), and a bandwidth of 20 MHz. The designed power amplifier was fabricated using the 180-nm RF CMOS process. The measured maximum linear output power was 17 dBm, whereas EVM was 5%.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.1
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• pp.20-26
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• 2016

This paper presents an X-band two-stage power amplifier using GaN-HEMT. Two-stage structure was adopted to take its high gain and simple inter-stage matching network. Based on a 3D EM simulation, the bond-wire inductance and the parasitic capacitance were predicted. By reducing bond-wire inductance, Q of the matching network is decreased and the bandwidth is improved. The implemented two-stage PA shows a power gain of more than 16 dB, saturated output power of more than 42.5 dBm, and a efficiency of more than 35 % in frequency range of 8.1~8.5 GHz with an operating voltage of 40 V.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.8
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• pp.880-886
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• 2007

We have proposed a new "hybrid" envelope elimination and restoration(EER) transmitter architecture using an efficiency optimized power amplifier(PA) and modified bias modulator. The efficiency of the PA at the average drain voltage is very important for the overall transmitter efficiency because the PA operates mostly at the average power region of the modulation signal. Accordingly, the efficiency of the PA has been optimized at the region. Besides, the bias modulator has been accompanied with the emitter follower for the minimization of memory effect. A saturation amplifier, class $F^{-1}$ is built using a 5-W PEP LDMOSFET for forward-link single-carrier wideband code-division multiple-access(WCDMA) at 1-GHz. For the interlock experiment, the bias modulator has been built with the efficiency of 64.16% and peak output voltage of 31.8 V. The transmitter with the proposed PA and bias modulator has been achieved an efficiency of 44.19%, an improvement of 8.11%. Besides, the output power is enhanced to 32.33 dBm due to the class F operation and the PAE is 38.28% with ACLRs of -35.9 dBc at 5-MHz offset. These results show that the proposed architecture is a very good candidate for the linear and efficient high power transmitter.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.8
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• pp.966-974
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• 2019

In this study, we propose a CMOS power amplifier (PA) using a bypass technique to enhance the efficiency in the low-power region. For the bypass structure, the common-gate (CG) transistor of the cascode structure of the driver stage is divided in two parallel branches. One of the CG transistors is designed to drive the power stage for high-power mode. The other CG transistor is designed to bypass the power stage for low-power mode. Owing to a turning-off of the power stage, the power consumption is decreased in low-power mode. The measured maximum output power is 20.35 dBm with a power added efficiency of 12.10%. At a measured output power of 11.52 dBm, the PAE is improved from 1.90% to 7.00% by bypassing the power stage. Based on the measurement results, we verified the functionality of the proposed bypass structure.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.4
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• pp.61-69
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• 2003

Cellular network을 이용하는 휴대 단말기의 경우 TDMA(GSM, IS-136), CDMA(IS-95) 그리고 WCD-MA 등을 포함해서 년간 약 4억대 정도 생산되고 있고, PAM(Power Amplifier Module)은 단말기 한 대당 1~2개 정도 사용되며, 단말기의 battery 사용시간과 밀접한 관련이 있다. 또한 antenna front-end에 장착되기 때문에, 신호의 왜곡에 의한 인접채널 누설 전력과 harmonic 등 전기적인 규격의 적합성과 ESD, 습기 등 품질 신뢰성 문제에 직접적인 영향을 주는 중요한 부품 중의 하나이다. 이로 인하여 PAM의 핵심 기능을 담당하는 PA IC의 공정 기술과 설계 기술, PAM제조 기술 등의 향상에 대한 많은 연구와 개발이 이루어졌다. 본 고에서는 PAM의 최근 기술 동향과 기능적으로 PAM이 주변 수동 및 능동 부품과 집적화 되고 있는 복합 모듈의 동향에 대해서 기술한다.

• Journal of Electrical Engineering and Technology
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• v.12 no.4
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• pp.1556-1565
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• 2017

This paper depicts the design, implementation and analysis of efficient resonant based wireless power transfer (WPT) technique using three magnetic coupled coils. This work is suitable for mid ranged device due to small form factor while minimizing the loading effect. A multi turned loop size resonator is exploited for both the transmitter and receiver for longer distance. In this paper, class-E power amplifier (class-E PA) is introduced with an optimum power tracking mechanism of WPT system to enhance the power capability at mid-range with a flat gain. A robust method of finding optimum distance is derived with an experimental analysis of the designed system. In this method, the load sensitive issue of WPT is resolved by tuning coupling coefficient at considerable distances. Our designed PA with a drain efficiency of 77.8% for a maximum output of 5W is used with adopted tuning technique that improves the overall WPT system performance by 3 dB at various operating points.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.2
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• pp.276-283
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• 2003

In this paper, a 2-stage power amplifier(PA) for IMT-2000 handset has been designed and fabricated using SiGe HBT, which has excellent frequency characteristics and linearity, to reduce size and weight instead of existing linearization techniques. DC I-V characteristics and S-parameter of SiGe HBT were simulated by Agilent circuit simulator(ADS), with large signal Gummel-Poon nonlinear circuit model. Then the output and interstage matching circuits were designed to satisfy the high power condition and the high gain condition, respectively. The experimental results showed output power of 27.1dBm and ACLR of 20dB, PAE of 34%, and linear power gain of 18.9dB over frequency ranges from 1920MHz to 1980MHz.