• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.29-36
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• 2000

The principle and design of two-stage CMOS operational amplifier with rail-to-rail input and class-AB output stage is presented. The rail-to-rail input stage shows almost constant transconductance independent of the common mode input voltage range in global transistor operation region. This new technique does not make use of accurate current-voltage relationship of MOS transistors. Hence it was achieved by using simple linear relationship of currents. The simulated transconductance variation using SPICE is less the 4.3%. The proposed global two-stage opamp can operate both in strong inversion and in weak inversion. Class AB output stage proposed also has a full output voltage swing and a well-defined quiescent current that does not depend on power supply voltage. Since feedback class- AB control is used, it is expected that this output stage can be operating in extremely low voltage. The variation of DC-gain and unity-gain frequency is each 4.2% and 12%, respectively.

• Journal of IKEEE
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• v.11 no.1 s.20
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• pp.69-76
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• 2007

This paper presents the design of LVDS (Low-Voltage-Differential-Signaling) transmitter for Gb/s-per-pin operation. The proposed LVDS transmitter is designed using BiCMOS technology, which can be compatible with CMOS technology. To reduce chip area and enhance the robustness of LVDS transmitter, the MOS switches of transmitter are replaced with lateral bipolar transistor. The common emitter current gain($\beta$) of designed bipolar transistor is 20 and the cell size of LVDS transmitter is $0.01mm^2$. Also the proposed LVDS driver is operated at 1.8V and the maximum data rate is 2.8Gb/s approximately In addition, a novel ESD protection circuit is designed to protect the ESD phenomenon. This structure has low latch-up phenomenon by using turn on/off character of P-channel MOSFET and low triggering voltage by N-channel MOSFET in the SCR structure. The triggering voltage and holding voltage are simulated to 2.2V, 1.1V respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.72-78
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• 2009

This paper proposes a low phase noise ring voltage controlled oscillator(VCO) with a standard $0.13{\mu}m$ CMOS process for PLL circuit using the VCO-gain-controlled Delay cell. The proposed Delay cell architecture with a active resistor using a MOS transistor. This method can reduced a VCO gain so that improve phase noise. And, Delay cell consist of Wide-Swing Cascode current mirror, Positive Latch and Symmetric load for low phase noise. The measurement results demonstrate that the phase noise is -119dBc/Hz at 1MHz offset from 1.9GHz. The VCO gain and power dissipation are 440MHz/V and 9mW, respectively.

• Journal of Sensor Science and Technology
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• v.12 no.4
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• pp.149-155
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• 2003

A PMOSFET photodetector for highly-sensitive active pixel sensor(APS) is presented. This sensor uses 5V power supply and has been designed and fabricated using I-poly and 2-metal $1.5{\mu}m$ CMOS technology. The feature of a PMOSFET photodetector is that the polysilicon gate of the PMOSFET was connected to n-well, in order to increase the photo sensitivity. The designed MOS photodetector has similar $I_{DS}-V_{DS}$ characteristics with a standard MOSFET. One dimensional image sensor with 16 pixels based on the PMOSFET photodetector has also been designed and fabricated. Unit pixel of the designed sensor consists of a PMOSFET photodetector and 4 NMOSFETs. Unit pixel area is $86{\mu}m{\times}90.5{\mu}m$ and its fill factor is about 12%.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.9
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• pp.808-812
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• 2006

In this dissertation, Ru-Zr metal gate electrode deposited on two kinds of dielectric were formed for MOS capacitor. Sample co-sputtering method was used as a alloy deposition method. Various atomic composition was achieved when metal film was deposited by controlling sputtering power. To study the characteristics of metal gate electrode, C-V(capacitance-voltage) and I-V(current-voltage) measurements were performed. Work function and equivalent oxide thickness were extracted from C-V curves by using NCSU(North Carolina State University) quantum model. After the annealing at various temperature, thermal/chemical stability was verified by measuring the variation of effective oxide thickness and work function. This dissertation verified that Ru-Zr gate electrodes deposited on $SiO_{2}\;and\;ZrO_{2}$ have compatible work functions for NMOS at the specified atomic composition and this metal alloys are thermally stable. Ru-Zr metal gate electrode deposited on $SiO_{2}\;and\;ZrO_{2}$ exhibit low sheet resistance and this values were varied with temperature. Metal alloy deposited on two kinds of dielectric proposed in this dissertation will be used in company with high-k dielectric replacing polysilicon and will lead improvement of CMOS properties.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.3
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• pp.159-167
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• 2005

Quantization effects (QEs), which manifests when the device dimensions are comparable to the de Brogile wavelength, are becoming common physical phenomena in the present micro-/nanometer technology era. While most novel devices take advantage of QEs to achieve fast switching speed, miniature size and extremely small power consumption, the mainstream CMOS devices (with the exception of EEPROMs) are generally suffering in performance from these effects. In this paper, an analytical model accounting for the QEs and poly-depletion effects (PDEs) at the silicon (Si)/dielectric interface describing the capacitance-voltage (C-V) and current-voltage (I-V) characteristics of MOS devices with thin oxides is developed. It is also applicable to multi-layer gate-stack structures, since a general procedure is used for calculating the quantum inversion charge density. Using this inversion charge density, device characteristics are obtained. Also solutions for C-V can be quickly obtained without computational burden of solving over a physical grid. We conclude with comparison of the results obtained with our model and those obtained by self-consistent solution of the $Schr{\ddot{o}}dinger$ and Poisson equations and simulations reported previously in the literature. A good agreement was observed between them.

• Korean Journal of Remote Sensing
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• v.4 no.1
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• pp.31-40
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• 1988

Low-cost microcomputer systems can be assembled which possess computing power, color display, memory, and storage capacity approximately equal to graphic workstactions. A low-cost, flexible, and user-friendly IBM/PC/XT/AT based image processing system has been developed and named as KMIPS(KAIST (Korea Advanced Institute of Science & Technology) Map and Image Processing Station). It can be easily utilized by the resource managers who are not computer specialists. This system can: * directly access Landsat MSS and TM, SPOT, NOAA AVHRR, MOS-1 satellite imagery and other imagery from different sources via magnetic tape drive connected with IBM/PC; * extract image up to 1024 line by 1024 column and display it up to 480 line by 672 column with 512 colors simultaneously available; * digitize photographs using a frame grabber subsystem(512 by 512 picture elements); * perform a variety of image analyses, GIS and terrain analyses, and display functions; and * generate map and hard copies to the various scales. All raster data input to the microcomputer system is geographically referenced to the topographic map series in any rater cell size selected by the user. This map oriented, georeferenced approach of this system enables user to create a very accurately registered(.+-.1 picture element), multivariable, multitemporal data sets which can be subsequently subsequently subjected to various analyses and display functions.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.62-68
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• 2010

This work proposes a 10b 100MS/s DAC based on a segmented local matching technique primarily for small chip area. The proposed DAC employing a segmented current-steering structure shows the required high linearity even with the small number of devices and demonstrates a fast settling behavior at resistive loads. The proposed segmented local matching technique reduces the number of current cells to be matched and the size of MOS transistors while a double-cascode topology of current cells achieves a high output impedance even with minimum sized devices. The prototype DAC implemented in a 0.13um CMOS technology occupies a die area of $0.13mm^2$ and drives a $50{\Omega}$ load resistor with a full-scale single output voltage of $1.0V_{p-p}$ at a 3.3V power supply. The measured DNL and INL are within 0.73LSB and 0.76LSB, respectively. The maximum measured SFDR is 58.6dB at a 100MS/s conversion rate.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.40-49
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• 2008

A Frequency synthesizer for mobile-DTV applications is implemented using $0.18{\mu}m$ CMOS process with 1.8V supply. PMOS transistors are chosen for VCO core to reduce phase noise. The measurement result of VCO frequency range is 800MHz-1.67GHz using switchable inductors, capacitors and varactors. We use varactor bias technique for the improvement of VCO gain linearity, and the number of varactor biasing are minimized as two. VCO gain deterioration is also improved by using the varactor switching technique. The VCO gain and interval of VCO gain are maintained as low and improved using the VCO frequency calibration block. The sigma-delta modulator for fractional divider is designed by the co-simualtion method for accuracy and efficiency improvement. The VCO, PFD, CP and LF are verified by Cadence Spectre, and the sigma-delta modulator is simulated using Matlab Simulink, ModelSim and HSPICE. The power consumption of the frequency synthesizer is 18mW, and the VCO has 52.1% tuning range according to the VCO maximum output frequency. The VCO phase noise is lower than -100dBc/Hz at 1MHz at 1MHz offset for 1GHz, 1.5GHz, and 2GHz output frequencies.