• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.8
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• pp.651-657
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• 2000

The notching effect in etching of undoped amorphous silicon gate had different characteristics and mechanism comparing with reported ones. The undoped amorphous silicon was etched by using HBr gas plasma. First in the region of small line width the potential increased as a result of ions in the exposed surface of oxide and the incident ions between the small line widths were deflected more wide range therefore the depth of notching was shallow and wide. Second in the region of large line width of gate electrons were charged on the top of photoresist and the side of gate a part of ions deflected. The deflected ions were partly charged positive on the side of gate and then these partly charged ions produced potential difference. Therefore ions stored up more at independent line than at dense line and notching became deeper by Br ion bombardments.

• Journal of IKEEE
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• v.27 no.4
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• pp.386-390
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• 2023

In this study, we examined the quasi-nonvolatile memory characteristics of silicon nanosheet (SiNS) feedback field-effect transistors (FBFETs) fabricated using a complementary metal-oxide-semiconductor process. The SiNS channel layers fabricated by photoresist overexposure method had a width of approximately 180 nm and a height of 70 nm. The SiNS FBFETs operated in a positive feedback loop mechanism and exhibited an extremely low subthreshold swing of 1.1 mV/dec and a high ON/OFF current ratio of 2.4×10⁷. Moreover, SiNS FBFETs represented long retention time of 50 seconds, indicating the quasi-nonvolatile memory characteristics.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.8 no.1
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• pp.37-44
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• 2015

In this paper, we have investigated a selective assembly method of single-walled carbon nanotubes (SWCNTs) on a silicon substrate using only photolithographic process and then proposed a fabrication method of field effect transistors (FETs) using SWCNT-based patterns. The aminopropylethoxysilane (APTES) patterns, which are formed for positively charged surface molecular patterns, are utilized to assemble and align millions of SWCNTs and we can more effectively assemble on a silicon (Si) surface using this method than assembly processes using only the 1-octadecyltrichlorosilane (OTS). We investigated a selective assembly method of SWCNTs on a Si surface using surface-programmed APTES and OTS patterns and then a fabrication method of FETs. photoresist(PR) patterns were made using photolithographic process on the silicon dioxide (SiO2) grown Si substrate and the substrate was placed in the OTS solution (1:500 v/v in anhydrous hexane) to cover the bare SiO2 regions. After removing the PR, the substrate was placed in APTES solution to backfill the remaining SiO2 area. This surface-programmed substrate was placed into a SWCNT solution dispersed in dichlorobenzene. SWCNTs were attracted toward the positively charged molecular regions, and aligned along the APTES patterns. On the contrary, SWCNT were not assembled on the OTS patterns. In this process, positively charged surface molecular patterns are utilized to direct the assembly of negatively charged SWCNT on SiO2. As a result, the selectively assembled SWCNT channels can be obtained between two electrodes(source and drain electrodes). Finally, we can successfully fabricate SWCNT-based multi-channel FETs by using our self-assembled monolayer method.

• Journal of Surface Science and Engineering
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• v.55 no.6
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• pp.460-468
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• 2022

Due to its high electrical conductivity, low contact resistance, good weldability and high corrosion resi-stance, gold is widely used in electronic components such as connectors and printed circuit boards (PCB). Gold ion salts currently used in gold plating are largely cyan-based salts and non-cyanic salts. The cya-nide bath can be used for both high and low hardness, but the non-cyanide bath can be used for low hardness plating. Potassium gold cyanide (KAu(CN)₂) as a cyanide type and sodium gold sulfite (Na₃[Au(SO)₃]₂) salt as a non-cyanide type are most widely used. Although the cyan bath has excellent performance in plating, potassium gold cyanide (KAu(CN)₂) used in the cyan bath is classified as a poison and a toxic substance and has strong toxicity, which tends to damage the positive photoresist film and make it difficult to form a straight side-wall. There is a need to supplement this. Therefore, it is intended to supplement this with an eco-friendly process using sodium sulfite sodium salt that does not contain cyan. Therefore, the main goal is to form a gold plating layer with a controllable hardness using a non-cyanide gold plating solution. In this study, the composition of a non-cyanide gold plating solution that maintains hardness even after annealing is generated through gold-palladium alloying by adding thallium, a crystal regulator among electrolysis factors affecting the structure and hardness, and changes in plating layer structure and crystallinity before and after annealing the correlation with the hardness.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.7
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• pp.33-39
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• 2015

In this work, SU-8 passivated IZO thin-film transistors(TFTs) made by solution-processes was investigated for enhancing stability of indium zinc oxide(IZO) TFT. A very viscous negative photoresist SU-8, which has high mechanical and chemical stability, was deposited by spin coating and patterned on top of TFT by photo lithography. To investigate the enhanced electrical performances by using SU-8 passivation layer, the TFT devices were analyzed by X-ray phtoelectron spectroscopy(XPS) and Fourier transform infrared spectroscopy(FTIR). The TFTs with SU-8 passivation layer show good electrical characterestics, such as ${\mu}_{FE}=6.43cm^2/V{\cdot}s$, $V_{th}=7.1V$, $I_{on/off}=10^6$, SS=0.88V/dec, and especially 3.6V of ${\Delta}V_{th}$ under positive bias stress (PBS) for 3600s. On the other hand, without SU-8 passivation, ${\Delta}V_{th}$ was 7.7V. XPS and FTIR analyses results showed that SU-8 passivation layer prevents the oxygen desorption/adsorption processes significantly, and this feature makes the effectiveness of SU-8 passivation layer for PBS.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 1999.10a
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• pp.49-49
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• 1999

In this study, $Cl_2/BCI_3$ magnetized inductively coupled plasmas (MICP) were used to etch GaN and the effects of magnetic confinements of inductively coupled plasmas on the GaN etch characteristics were investigated as a function of $Cl_2/BCI_3$. Also, the effects of Kr addition to the magnetized $Cl_2/BCI_3$ plasmas on the GaN etch rates were investigated. The characteristics of the plasmas were estimated using a Langmuir probe and quadrupole ma~s spectrometry (QMS). Etched GaN profiles were observed using scanning electron microscopy (SEM). The small addition of $Cl_2/BCI_3$ (10-20%) in $Cl_2$ increased GaN etch rates for both with and without the magnetic confinements. The application of magnetic confinements to the $Cl_2/BCI_3$ inductively coupled plasmas (ICP) increased GaN etch rates and changed the $Cl_2/BCI_3$ gas composition of the peak GaN etch rate from 10% $BCI_3$ to 20% $BCI_3$. It also increased the etch selectivity over photoresist, while slightly reducing the selectivity over $Si0_2$. The application of the magnetic field significantly increased positive $BCI_2{\;}^+$ measured by QMS and total ion saturation current measured by the Langmuir probe. Other species such as CI, BCI, and CI+ were increased while species such as $BCl_2$ and $BCI_3$ were decreased with the application of the magnetic field. Therefore, it appears that the increase of GaN etch rate in our experiment is related to the increased dissociative ionization of $BCI_3$ by the application of the magnetic field. The addition of 10% Kr in an optimized $Cl_2/BCI_3$ condition (80% $Cl_2/$ 20% $BCI_3$) with the magnets increased the GaN etch rate about 60%. More anisotropic GaN etch profile was obtained with the application of the magnetic field and a vertical GaN etch profile could be obtained with the addition of 10% Kr in an optimized $Cl_2/BCI_3$ condition with the magnets.