• Journal of Sensor Science and Technology
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• v.16 no.4
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• pp.319-323
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• 2007

This paper describes the mechanical characteristics of poly 3C-SiC thin films grown on Si wafers with thermal oxide. In this work, the poly 3C-SiC thin film was deposited by APCVD method using only Ar carrier gas and single precursor HMDS at $1100^{\circ}C$. The elastic modulus and hardness of poly 3C-SiC thin films were measured using nanoindentation. Also, the roughness of surface was investigated by AFM. The resulting values of elastic modulus E, hardness H and the roughness of the poly 3C-SiC film are 305 GPa, 26 GPa and 49.35 nm respectively. The mechanical properties of the grown poly 3C-SiC film are better than bulk Si wafers. Therefore, the poly 3C-SiC thin film is suitable for abrasion, high frequency and MEMS applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.125-126
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• 2007

Polycrystalline silicon thin-film-transistors (Poly-Si TFT's) with a amorphous-$Si_xGe_y$ seed layer have been fabricated to improve the performance of TFT. The dependence of crystal structure and electrical characteristics on the the Ge fractions in $Si_xGe_y$ seed layer were investigated. As a result, the increase of grain size and enhancement of electrical characteristics were obtained from the poly-Si TFT's with amorphous-SixGey seed layer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.93-94
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• 2007

다양한 LDD(lightly doped drain)에 따른 n-channel poly-Si TFT (thin film transistor)에 대하여 보고한다. 유리 기판 위에 ELA를 이용하여 만들어진 Polycrystalline silicon (poly-Si)은 TFT-LCD의 응용을 위한 재료로써 우수한 특성을 갖는다. 제작된 n-channel TFT는 절연층으로 $SiN_x$, $SiO_2$의 이중 구조를 갖는다. 다양한 LDD에 따른 n-channel poly-Si TFT의 문턱전압($V_{TH}$), ON/OFF 전류비 ($I_{ON}/I_{OFF}$), 포화전류($I_{DSAT}$)는 TFT의 보다 좋은 성능을 위해 연구된다. 짧은 LLD 길이를 가진 n-channel poly-Si TFT의 문턱전압은 작고, 포화전류의 값은 크다. 또한 긴 LLD 길이를 가진 n-channel poly-Si TFT는 작은 kink effect를 가진다.

• Journal of the Korean institute of surface engineering
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• v.33 no.4
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• pp.217-221
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• 2000

The gate oxide thickness is becoming thinner and thinner in order to speed up the semiconductor CMOS devices. We have investigated very thin$ SiO_2$ gate oxide layers and found anomaly between the thickness determined with capacitance measurement and these obtained with cross-sectional high resolution transmission electron microscopy. The thicknesses difference of the two becomes important for the thickness of the oxide below 5nm. We propose that the variation of dielectric constant in thin oxide films cause the anomaly. We modeled the behavior as (equation omitted) and determined $\varepsilon_{bulk}$=3.9 and $\varepsilon_{int}$=-4.0. We predict that optimum $SiO_2$ gate oxide thickness may be $20\AA$ due to negative contribution of the interface dielectric constant. These new results have very important implication for designing the CMOS devices.s.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.1
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• pp.35-40
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• 1997

A new method to form the gate oxide and recrystllize the polycrystalline silicon (poly-Si) active layer simultaneously is proposed and fabricated successfully. During te irradiation of excimer laser, the poly-Si film is recrystallized, while the oxygen ion impurities injected into the amorphous silicon(a-Si) film are activated by laser energy and react with silicon atoms to form SiO2. We investigated the characteristics of the sample fabricated by proposed method using AES, TEM, AFM. The electrical performance of oxide was verified by ramp up voltage method. Our experimental results show that a high quality oxide, a pol-Si film with fine grain, and a smooth and clean interface between oxide and poly-Si film have been successfully obtained by the proposed fabrication method. The interface roughness of oxide/poly-Si fabricated by new method is superior to film by conventional fabrication os that the proposed method may improve the performance of poly-Si TFTs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.93-93
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• 2008

This paper presents the Raman scattering characteristics of poly (polycrystalline) 3C-SiC thin films deposited on AlN buffer layer by atmospheric pressure chemical vapor deposition (APCVD) using hexamethyldisilane (MHDS) and carrier gases (Ar + $H_2$).The Raman spectra of SiC films deposited on AlN layer of before and after annealings were investigated according to the growth temperature of 3C-SiC. Two strong Raman peaks, which mean that poly 3C-SiC admixed with nanoparticle graphite, were measured in them. The biaxial stress of poly 3C-SiC/AlN was calculated as 896 MPa from the Raman shifts of 3C-SiC deposited at $1180^{\circ}C$ on AlN of after annealing.

• Korean Journal of Materials Research
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• v.1 no.3
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• pp.125-131
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• 1991

Boron penetration phenomenon of $p^{+}$ silicon gate with as-deposited amorphous or polycrystalline Si upon high temperature annealing was investigated using high frequency C-V (Capacitance-Volt-age) analysis, CCST(Constant Current Stress Test), TEM(Transmission Electron Microscopy) and SIMS(Secondary Ion Mass Spectroscopy), C-V analysis showed that an as-deposited amorphous Si gate resulted in smaller positive shifts in flatband voltage compared wish a polycrystalline Si gate, thus giving 60-80 percent higher charge-to-breakdown of gate oxides. The reduced boron penetration of amorphous Si gate may be attributed to the fewer grain boundaries available for boron diffusion into the gate oxide and the shallower projected range of $BF_2$ implantation. The relation between electron trapping rate and flatband voltage shift was also discussed.

• Journal of the Korean Vacuum Society
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• v.17 no.2
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• pp.130-137
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• 2008

$La_{0.7}Sr_{0.3}MnO_3$ films were deposited on $SiO_2$/Si and Si substrates annealed at $350^{\circ}C$ by rf magnetron sputtering. The oxygen gas flow rates were varied as 0, 40, and 80 sccm. Without post annealing process, $La_{0.7}Sr_{0.3}MnO_3$ thin films on $SiO_2$/Si and Si substrates were polycrystalline with (100), (110), and (200) growth planes. The grain size of $La_{0.7}Sr_{0.3}MnO_3$ thin films was increased with increasing oxygen gas flow rate. The sheet resistance of $La_{0.7}Sr_{0.3}MnO_3$ thin films was decreased with oxygen flow rate due to the increased grain size which induced a reduction of grain boundary. TCR (temperature coefficient of resistance) values of $La_{0.7}Sr_{0.3}MnO_3$ thin films were obtained from -2.0% to -2.2%.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2007.06a
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• pp.183-187
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• 2007

The magnetron reactive ion etching (RIE) characteristics of polycrystalline (poly) 3C-SiC grown on $SiO_2$/Si substrate by APCVD were investigated. Poly 3C-SiC was etched by $CHF_3$ gas, which can form a polymer as a function of side wall protective layers, with additive $O_2$ and Ar gases. Especially, it was performed in magnetron RIE, which can etch SiC at lower ion energy than a commercial RIE system. Stable etching was achieved at 70 W and the poly 3C-SiC was undamaged. The etch rate could be controlled from $20\;{\AA}/min$ to $400\;{\AA}/min$ by the manipulation of gas flow rates, chamber pressure, RF power, and electrode gap. The best vertical structure was improved by the addition of 40 % $O_2$ and 16 % Ar with the $CHF_3$ reactive gas. Therefore, poly 3C-SiC etched by magnetron RIE can expect to be applied to M/NEMS applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.129-130
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• 2008

Polycrystalline silicon (poly-Si) Schottky barrier thin film transistors (SB-TFT) are fabricated by erbium silicided source/drain for n-type SB-TFT. High quality poly-Si film were obtained by crystallizing the amorphous Si film with excimer laser annealing (ELA) or solid phase crystallization (SPC) method. The fabricated poly-Si SB-TFTs have a large on/off current ratio with a low leakage current. Moreover, the electrical characteristics of poly-Si SB TFTs are significantly improved by the additional forming gas annealing in 2 % $H_2/N_2$, because the interface trap states at the poly-Si grain boundaries and at the gate oxide/poly-Si channel decreased.