• Proceedings of the KIEE Conference
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• 1998.11c
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• pp.1001-1003
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• 1998

In this paper, $Ar^+$ ion laser etching process of single/poly crystalline silicon with $CCl_{2}F_{2}$ gas is studied for MEMS applications. To investigate the effects of process parameters, laser power, gas pressure, scanning speed were varied and multiple scanning was carried out to obtain high aspect ratio. In addition, scanning width was varied to observe the trench profile etched in repeating scanning cycle. From the etching of $2.6{\mu}m$ thick polycrystalline Si deposited on insulator, trench with flat bottom and vertical side wall was obtained and it is possible to apply this results for MEMS applications.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.313-313
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• 2013

For high-performance TFT (Thin film transistor), poly-crystalline semiconductor thin film with low resistivity and high hall carrier mobility is necessary. But, conventional SPC (Solid phase crystallization) process has disadvantages in fabrication such as long annealing time in high temperature or using very expensive Excimer laser. On the contrary, MIC (Metal-induced crystallization) process enables semiconductor thin film crystallization at lower temperature in short annealing time. But, it has been known that the poly-crystalline semiconductor thin film fabricated by MIC methods, has low hall mobility due to the residual metals after crystallization process. In this study, Ni metal was shallow implanted using PIII&D (Plasma Immersion Ion Implantation & Deposition) technique instead of depositing Ni layer to reduce the Ni contamination after annealing. In addition, the effect of external magnetic field during annealing was studied to enhance the amorphous silicon thin film crystallization process. Various thin film analytical techniques such as XRD (X-Ray Diffraction), Raman spectroscopy, and XPS (X-ray Photoelectron Spectroscopy), Hall mobility measurement system were used to investigate the structure and composition of silicon thin film samples.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.2
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• pp.55-62
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• 1992

Polycrystalline silicon ingots were manufactured using the casting method for polycrystalline silicon solar cells. These ingots were cut into wafers and ten n$^{+}$p type solar cells were made through the following simple process` surface etching, n$^{+}$p junction formation, metalization and annealing. For the grain boundary passivation, the samples were oxidized in O$_2$ for 5 min. at 80$0^{\circ}C$ prior to diffusion in Ar for 100 min. at 95$0^{\circ}C$. The conversion efficiency of polycrystalline silicon solar cells made from these wafers showed about 70-80% of those of the single crystalline silicon solar cell and superior conversion efficiency, compared to those of commercial polycrystalline wafers of Wacker Chemie. The maximum conversion efficiency of our wafers was indicated about 8%(without AR coating) in spite of such a simple fabrication method.

• Journal of Energy Engineering
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• v.21 no.3
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• pp.243-248
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• 2012

In this study, The report analysed the characteristics of power drop and damage of surface in solar cell through high temperature and humidity test. The solar cells were tested during the 1000hr in $85^{\circ}C$ temperature and 85% humidity conditions, that excerpted standard of PV Module(KS C IEC-61215). An analysis of the cell surface through EL(Electroluminescence), the cell has partly change of surface in yearly. Single-crystalline Solar cell efficiency is decreased from 17.7% to 15.6% and decreasing rate is 11.9%. On the other hand, Poly-crystalline Solar cell efficiency is decreased from 15.5% to 14.0% and decreasing rate is 9.3%. A comparison of the fill factor for analysis of electro characteristic in yearly, Single-crystalline Solar cell efficiency is decreased from 78.7% to 78.1% and decreasing rate is 4.7%. On the other hand, Poly-crystalline Solar cell efficiency is decreased from 78.1% to 76.7% and decreasing rate is 1.8%. Single-crystalline has more bigger power drop than poly-crystalline by the silicon purity and silicon atom arrangement. Also, FF decreasing rate has more bigger drop than efficiency decreasing rate for the reason that the damage of surface by exterior environmental factor is the more influence in cell than other reason that is decreasing FF by damage of p-n junction.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1427-1429
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• 2001

Polycrystalline silicon(poly-Si) films are deposited on low temperature glass substrate by Hot-Wire CVD(HWCVD). The structural properties of the poly-Si films are strongly dependent on the wire temperature($T_w$). The films deposited at high $T_w$ of 2000$^{\circ}C$ have superior crystalline properties; average lateral grain sizes are larger than $1{\mu}m$ and there at·e no vertical grain boundaries. The surface of the high $T_w$ samples are naturally textured like pyramid shape. These large grain size and textured surface are believed to give high current density when applied to solar cells. However, the poly-si films are structurally porous and contains high defect density, by which high concentration of C and O resulted within the films by air-penetration after removed from chamber.

• Journal of the Korean Solar Energy Society
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• v.21 no.1
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• pp.1-10
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• 2001

Polycrystalline silicon(poly-Si) films are deposited on low temperature glass substrate by Hot-CVD(HWCVD). The structural properties of the poly-Si films are strongly dependent on the temperature$(T_w)$. The films deposited at high $T_w$ of $2000^{\circ}C$ have superior crystalline proper average lateral grain sizes are larger than $1{\mu}m$ and there are no vertical grain boundaries. The sur of the high $T_w$ samples are naturally textured like pyramid shape. These large grain size and text surface are believed to give high current density when applied to solar cells. However, the poly films are structurally porous and contains high defect density, by which high concentration of C and O resulted within the films by air-penetration after removed from chamber.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.3 no.1
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• pp.59-65
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• 1993

The boron-doped polycrystalline silicon films which can be used in pressure sensors were fabricated in a high-vacuum resistance heating evaporator. Poly-Si films were deposited on quartz substrates at various temperatures and the boron was doped to the silicon film in a diffusion furnace using BN wafer. The silicon films deposited at $500^{\circ}C$ was amorphous, began to show crystalline at $600^{\circ}C$, and became polycrystalline at $700^{\circ}C$. After doping boron at $900^{\circ}C$for 10 minutes, the resistivity of the films was in the range of $0.1{\Omega}cm~1.5{\Omega}cm$, the boron density was $9.4\times10^{15}~2.1\times{10}^{17}cm^{-3}$, and the grain size was $107{\AA}~191{\AA}$.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1050-1053
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• 2002

In this paper, Amorphous silicon on glass substrate was recrystallized to poly-crystalline silicon by solid phase crystallization (SPC) technology. The active region of thin film transistor (TFT) was fabricated by amorphous silicon. The output and transfer characteristics of thin film transistor with lightly doped drain (LDD) structure was measured and analyzed. As a results, analyzed TFTs reliability with LDD's length by various kinds argument such as sub-threshold swing coefficient, mobility and threshold voltages were evaluated. Stress effects in TFT were able to improve to the characteristics of turn-on current and hot carrier effects by LDD's length variations.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.185-188
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• 2002

In this paper, Amorphous silicon on glass substrate was recrytallized to poly-crystalline silicon by solid phase crystallization(SPC) technology The active region of thin film transistor(TFT) was fabricated by amorphous silicon. The output and transfer characteristics of thin film transistor with lightly doped drain(LDD) structure was measured and analyzed. As a results, analyzed TFT's reliability with LDD's length by various kinds argument such as sub-threshold swing coefficient, mobility and threshold voltages were evaluated. Stress effects in TFT were able to improve to the characteristics of turn-on current and hot carrier effects by LDD's length variations

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.2
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• pp.112-115
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• 2011

To stabilize the electric characteristic of Silicon Thin Film Transistor, reducing the current leakage is most important issue. To reduce the current leakage, many ideas were suggested. But the increase of mask layer also increased the cost. On this research Bird's Beak process was use to present element. Using Silvaco simulator, it was proven that it was able to reduce current leakage without mask layer. As a result, it was possible to suggest the structure that can reduce the current leakage to 1.39nA without having mask layer increase. Also, I was able to lead the result that electric characteristic (on/off current ratio) was improved compare from conventional structure.