• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.255-255
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• 2010

Recently, nonvolatile memories (NVM) of various types have been researched to improve the electrical performance such as program/erase voltages, speed and retention times. Also, the charge trap memory is a strong candidate to realize the ultra dense 20-nm scale NVM. Furthermore, the high charge efficiency and the thermal stability of SiC nanocrystals NVM with single $SiO_2$ tunnel barrier have been reported. [1-2] In this study, the SiC charge trap NVM was fabricated and electrical properties were characterized. The 100-nm thick Poly-Si layer was deposited to confined source/drain region by using low-pressure chemical vapor deposition (LP-CVD). After etching and lithography process for fabricate the gate region, the $Si_3N_4/SiO_2/Si_3N_4$ (NON) and $SiO_2/Si_3N_4/SiO_2$ (ONO) barrier engineered tunnel layer were deposited by using LP-CVD. The equivalent oxide thickness of NON and ONO tunnel layer are 5.2 nm and 5.6 nm, respectively. By using ultra-high vacuum magnetron sputtering with base pressure 3x10-10 Torr, the 2-nm SiC and 20-nm $SiO_2$ were successively deposited on ONO and NON tunnel layers. Finally, after deposited 200-nm thick Al layer, the source, drain and gate areas were defined by using reactive-ion etching and photolithography. The lengths of squire gate are $2\;{\mu}m$, $5\;{\mu}m$ and $10\;{\mu}m$. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer, E4980A LCR capacitor meter and an Agilent 81104A pulse pattern generator system. The electrical characteristics such as the memory effect, program/erase speeds, operation voltages, and retention time of SiC charge trap memory device with barrier engineered tunnel layer will be discussed.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.781-784
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• 2005

Twenty four types of thermopile for micro spectrometer infrared sensors were fabricated on low-stress $Si_3N_4$ membranes with $1.2{\mu}m-thickness$ using MEMS technology. Poly-Si thin film with thickness of 3500 ${\AA}$ as the first thermocouple material, was deposited by LPCVD method. And aluminum thin film with thickness of 6000 ${\AA}$ as the second thermocouple material, was deposited by sputtering method. Thermopile were designed and fabricated for optimum conditions by five parameters of thermocouple numbers (16 ${\sim}$ 48), thermocouple line widths (10 ${\mu}m$ ${\sim}$ 25 ${\mu}m$), thermocouple lengths (100 ${\mu}m$ ${\sim}$ 500 ${\mu}m$), membrane areas ($1^2\;mm^2$ ${\sim}$ $2.5^2\;mm^2$) and junction areas (150 ${\mu}m^2$ ${\sim}$ 750 ${\mu}m^2$), respectively. Electromotive forces of fabricated thermopile were measured 1.1 mV ${\sim}$ 7.4 mV at $400^{\circ}C$. It was thought that measurement results could be used for thermopile infrared sensors optimum structure for micro spectrometers.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.957-960
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• 2009

Sensor applications of thin-film transistors (TFTs), such as photosensor, magnetic sensor, temperature sensor and chemical sensor, are introduced. Active-matrix circuits and amplifying circuits using poly-Si TFTs are integrated with these sensors to improve sensor performances and generate additional functions. These sensors may be promising applications after flat-panel displays (FPDs) in giant-micro electronics.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1116-1118
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• 2005

We studied laser crystallization of amorphous silicon films prepared at ultra low temperatures ($<150^{\circ}C$). Amorphous silicon films having a low content of hydrogen were deposited by using catalytic chemical vapor deposition method. Influence of process parameters on the hydrogen content was investigated. Laser crystallization was performed dispensing with the preliminary dehydrogenation process. Crystallization took place at a laser energy density value as low as $70\;mJ/cm^2$, and the grain size increased with increasing the laser energy. The ELA crystallization of Catalytic CVD a-Si film is a promising candidate for Poly-Si TFT in active-matrix flexible display on plastic substrates.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.25-28
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• 1999

Metal ferroelectric semiconductor Field Effect- Transistors(MFSFET) with various gate electrodes, that are aluminum, platinum and poly -Si, using LiNbO$_3$/Si(100) structures were fabricated and the properties of the FETs have been discussed. The drain current of the state of FET with Pt electrode was more than 3 orders of magnitude larger than the state current at the same gate voltage of 1.5 V, 7.rich means the memory operation of the MFSFET. A write voltage as low as about $\pm$4 V, which is applicable to low power integrated circuits, was used for polarization reversal. The retention properties of the FET using Al electrode were quite good up to about 10$^3$s and using Pt electrode remained almost the same value of its initial value over 2 days at room temperature.

• The Korean Journal of Ceramics
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• v.6 no.2
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• pp.138-142
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• 2000

Thin film $LiNbO_3$MFS (metal-ferroelectric-semiconductor) capacitor showed improved characteristics such as low interface trap density, low interaction with Si substrate, and large remanent polarization. This paper reports ferroelectric $LiNbO_3$thin films grown directly on p-type Si (100) substrates by 13.56 MHz RF magnetron sputtering system for FRAM (ferroelectric random access memory) applications. RTA (rapid thermal anneal) treatment was performed for as-deposited films in an oxygen atmosphere at $600^{\circ}C$ for 60sec. We learned from X-ray diffraction that the RTA treated films were changed from amorphous to poly-crystalline $LiNbO_3$which exhibited (012), (015), (022), and (023) plane. Low temperature film growth and post RTA treatments improved the leakage current of $LiNbO_3$films while keeping other properties almost as same as high substrate temperature grown samples. The leakage current density of $LiNbO_3$films decreased from $10^{-5}$ to $10^{-7}$A/$\textrm{cm}^2$ after RTA treatment. Breakdown electric field of the films exhibited higher than 500 kV/cm. C-V curves showed the clockwise hysteresis which represents ferroelectric switching characteristics. Calculated dielectric constant of thin film $LiNbO_3$illustrated as high as 27.9. From ferroelectric measurement, the remanent polarization and coercive field were achieved as 1.37 $\muC/\textrm{cm}^2$ and 170 kV/cm, respectively.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.388-388
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• 2016

Chemical mist deposition (CMD) of poly(3,4-ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS) was investigated with cavitation frequency f, solvent, flow rate of nitrogen, substrate temperature $T_s$, and substrate dc bias $V_s$ as variables for efficient PEDOT:PSS/crystalline (c-)Si heterojunction solar cells (Fig. 1). The high-speed camera and differential mobility analysis characterizations revealed that average size and flux of PEDOT:PSS mist depend on f, solvent, and $V_s$. The size distribution of mist particles including EG/DI water cosolvent is also shown at three different $V_s$ of 0, 1.5, and 5 kV for a f of 3 MHz (Fig. 2). The size distribution of EG/DI water mist without PEDOT:PSS is also shown at the bottom. A peak maximum shifted from 300-350 to 20-30 nm with a narrow band width of ~150 nm for PEDOT:PSS solution, whose maximum number density increased significantly up to 8000/cc with increasing $V_s$. On the other hand, for EG/water cosolvent mist alone, the peak maximum was observed at a 72.3 nm with a number density of ~700/cc and a band width of ~160 nm and it decreased markedly with increasing $V_s$. These findings were not observed for PEDOT:PSS/EG/DI water mist. In addition, the Mie scattering image of PEDOT:PSS mist under white bias light was not observed at $V_s$ above 5 kV, because the average size of mist became smaller. These results imply that most of solvent is solvated in PEDOT:PSS molecule and/or solvent is vaporized. Thus, higher f and $V_s$ generate preferentially fine mist particle with a narrower band width. Film deposition occurred when $V_s$ was impressed on positive to a c-Si substrate at a Ts of $30-40^{\circ}C$, whereas no deposition of films occurred on negative, implying that negatively charged mist mainly provide the film deposition. The uniform deposition of PEDOT:PSS films occurred on textured c-Si(100) substrate by adjusting $T_s$ and $V_s$. The adhesion of CMD PEDOT:PSS to c-Si enhanced by $V_s$ conspicuously compared to that of spin-coated film. The CMD PEDOT:PSS/c-Si solar cell devices on textured c-Si(100) exhibited a ${\eta}$ of 11.0% with the better uniformity of the solar cell parameters. Furthermore, ${\eta}$ increased to 12.5% with a $J_{sc}$ of $35.6mA/cm^2$, a $V_{oc}$ of 0.53 V, and a FF of 0.67 with an antireflection (AR) coating layer of 20-nm-thick CMD molybdenum oxide $MoO_x$ (n= 2.1) using negatively charged mist of 0.1 wt% 12 Molybdo (VI) phosphoric acid n-Hydrate) $H_3(PMo_{12}O_40){\cdot}nH_2O$ in methanol. CMD. These findings suggest that the CMD with negatively charged mist has a great potential for the uniform deposition of organic and inorganic on textured c-Si substrate by adjusting $T_s$ and $V_s$.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.279.1-279.1
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• 2016

박막 트랜지스터 (thin film transistor, TFT)는 고밀도, 대면적화로 높은 전자의 이동도가 요구되면서, 비정질 실리콘 (a-Si)에서 다결정 실리콘 (poly-Si) TFT 로 연구되었다. 이에 따라 비정질 실리콘에서 결정질 실리콘으로의 상변화에 대한 결정화 연구가 활발히 진행되었다. 또한, 박막 태양전지 분야에서도 유리기판 위에 비정질 층을 증착한 후에 열처리를 통해 상변화하는 고상 결정화 (solid-phase crystallization, SPC) 기술을 적용하여, CSG (thin-film crystalline silicon on glass) 태양전지를 보고하였다. 이러한 비정질 실리콘 층의 결정화 기술을 결정질 실리콘 태양전지 에미터 형성 공정에 적용하고자 한다. 이 때, 플라즈마화학증착 (Plasma-enhanced chemical vapor deposition, PECVD) 장비로 증착된 비정질 실리콘 층의 열처리를 통한 결정화 정도가 중요한 요소이다. 따라서, 비정질 실리콘 층의 결정화에 영향을 주는 인자에 대해 연구하였다. 비정질 실리콘 증착 조건(H2 가스 비율, 도펀트 유무), 실리콘 기판의 결정방향, 열처리 온도에 따른 결정화 정도를 엘립소미터(elipsometer), 투과전자현미경 (transmission electron microscope, TEM), 적외선 분광기 (Fourier Transform Infrared, FT-IR) 측정을 통하여 비교 하였다. 이를 기반으로 결정화 온도에 따른 비정질 실리콘의 결정화를 위한 활성화 에너지를 계산하였다. 비정질 실리콘 증착 조건 보다 기판의 결정방향이 결정화 정도에 크게 영향을 미치는 것으로 확인하였다.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.111-121
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• 2012

In this paper, a poly-Si thin film transistor with ${\sim}0.5{\mu}m$ gate length was fabricated and its electrical characteristics are optimized. From the results, it was verified that making active region with larger grain size using low temperature annealing is an efficient way to enhance the subthreshold swing, drain-induced barrier lowering and on-current characteristics. A SONOS flash memory was fabricated using this poly-Si channel process and its performances are analyzed. It was necessary to optimize O/N/O thickness for the reduction of electron back tunneling and the enhancement of its memory operation. The optimized device showed 2.24 V of threshold voltage memory windows which coincided with a well operating flash memory.

• Polymer(Korea)
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• v.36 no.3
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• pp.302-308
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• 2012

The objective of this study is to investigate optimum reaction conditions for the grafting of poly($N$-vinyl- 2-pyrrolidone) (PVP) onto the surface of plasma-treated polypropylene film. The plasma treatment conditions were fixed as 200 W rf power, 6 LPM Ar flow rate, 30 sec treatment time, and 5 min exposure time after treatment. For graft copolymerization, we investigated the change of grafting degree with respect to reaction time, reaction temperature and $N$-vinyl-2-pyrrolidone concentration. Maximum grafting degree was obtained at the conditions of 6 h reaction time, $90^{\circ}C$ reaction temperature, and 40% $N$-vinyl-2-pyrrolidone concentration. The introduction of PVP was confirmed by ATR-FTIR, XPS, and SEM analysis.