• Title/Summary/Keyword: poly silicon

Search Result 511, Processing Time 0.034 seconds

Synthesis of β-SiC Powder using a Recycled Graphite Block as a Source (그라파이트 블록을 원료로써 재활용한 β-SiC 분말 합성)

  • Nguyen, Minh Dat;Bang, Jung Won;Kim, Soo-Ryoung;Kim, Younghee;Jung, Eunjin;Hwang, Kyu Hong;Kwon, Woo-Teck
    • Resources Recycling
    • /
    • v.26 no.1
    • /
    • pp.16-21
    • /
    • 2017
  • This paper relates to the synthesis of a source powder for SiC crystal growth. ${\beta}-SiC$ powders are synthesized at high temperatures (>$1400^{\circ}C$) by a reaction between silicon powder and carbon powder. The reaction is carried out in a graphite crucible operating in a vacuum ambient (or Ar gas) over a period of time sufficient to cause the Si+C mixture to react and form poly-crystalline SiC powder. End-product characterizations are pursued with X-ray diffraction analysis, SEM/EDS, particle size analyzer and ICP-OES. The purity of the end-product was analyzed with the Korean Standard KS L 1612.

MASK ROM IP Design Using Printed CMOS Process Technology (Printed CMOS 공정기술을 이용한 MASK ROM 설계)

  • Jang, Ji-Hye;Ha, Pan-Bong;Kim, Young-Hee
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 2010.05a
    • /
    • pp.788-791
    • /
    • 2010
  • We design 64-bit ROM IP for RFID tag chips using printed CMOS non-volatile memory IP design technology for a printed CMOS process. The proposed 64-bit ROM circuit is using ETRI's $0.8{\mu}m$ CMOS porocess, and is expected to reduce process complexity and cost of RFID tag chips compared to that using a conventional silicon fabrication based on a complex lithography process because the poly layer in a gate terminal is using printing technology of imprint process. And a BL precharge circuit and a BL sense amplifier is not required for the designed cell circuit since it is composed of a transmission gate instead of an NMOS transistor of the conventional ROM circuit. Therefore an output datum is only driven by a DOUT buffer circuit. The Operation current and layout area of the designed ROM of 64 bits with an array of 8 rows and 8 columns using $0.8{\mu}m$ ROM process is $9.86{\mu}A$ and $379.6{\times}418.7{\mu}m^2$.

  • PDF

Nanoscale quantitative mechanical mapping of poly dimethylsiloxane in a time dependent fashion

  • Zhang, Shuting;Ji, Yu;Ma, Chunhua
    • Advances in nano research
    • /
    • v.10 no.3
    • /
    • pp.253-261
    • /
    • 2021
  • Polydimethylsiloxane (PDMS) is one of the most widely adopted silicon-based organic polymeric elastomers. Elastomeric nanostructures are normally required to accomplish an explicit mechanical role and correspondingly their mechanical properties are crucial to affect device and material performance. Despite its wide application, the mechanical properties of PDMS are yet fully understood. In particular, the time dependent mechanical response of PDMS has not been fully elucidated. Here, utilizing state-of-the-art PeakForce Quantitative Nanomechanical Mapping (PFQNM) together with Force Volume (FV) and Fast Force Volume (FFV), the elastic moduli of PDMS samples were assessed in a time-dependent fashion. Specifically, the acquisition frequency was discretely changed four orders of magnitude from 0.1 Hz up to 2 kHz. Careful calibrations were done. Force data were fitted with a linearized DMT contact mechanics model considering surface adhesion force. Increased Young's modulus was discovered with increasing acquisition frequency. It was measured 878 ± 274 kPa at 0.1 Hz and increased to 4586 ± 758 kPa at 2 kHz. The robust local probing of mechanical measurement as well as unprecedented high-resolution topography imaging open new avenues for quantitative nanomechanical mapping of soft polymers, and can be extended to soft biological systems.

A 1280-RGB $\times$ 800-Dot Driver based on 1:12 MUX for 16M-Color LTPS TFT-LCD Displays (16M-Color LTPS TFT-LCD 디스플레이 응용을 위한 1:12 MUX 기반의 1280-RGB $\times$ 800-Dot 드라이버)

  • Kim, Cha-Dong;Han, Jae-Yeol;Kim, Yong-Woo;Song, Nam-Jin;Ha, Min-Woo;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.46 no.1
    • /
    • pp.98-106
    • /
    • 2009
  • This work proposes a 1280-RGB $\times$ 800-Dot 70.78mW 0.l3um CMOS LCD driver IC (LDI) for high-performance 16M-color low temperature poly silicon (LTPS) thin film transistor liquid crystal display (TFT-LCD) systems such as ultra mobile PC (UMPC) and mobile applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed LDI optimizes power consumption and chip area at high resolution based on a resistor-string based architecture. The single column driver employing a 1:12 MUX architecture drives 12 channels simultaneously to minimize chip area. The implemented class-AB amplifier achieves a rail-to-rail operation with high gain and low power while minimizing the effect of offset and output deviations for high definition. The supply- and temperature-insensitive current reference is implemented on chip with a small number of MOS transistors. A slew enhancement technique applicable to next-generation source drivers, not implemented on this prototype chip, is proposed to reduce power consumption further. The prototype LDI implemented in a 0.13um CMOS technology demonstrates a measured settling time of source driver amplifiers within 1.016us and 1.072us during high-to-low and low-to-high transitions, respectively. The output voltage of source drivers shows a maximum deviation of 11mV. The LDI with an active die area of $12,203um{\times}1500um$ consumes 70.78mW at 1.5V/5.5V.

Apoptosis Induced by BARODON® in Human Gastric Cancer Cells (BARODON® 에 의한 Human Gastric Adenocarcinoma AGS 세포고사)

  • Jo Eun-Hye;Choi Soo-Il;Kim Soo-Rim;Cho Sung-Dae;Ahn Nam-Shic;Jung Ji-Won;Yang Se-Ran;Park Joon-Suk;Hwang Jae-Woong;Park Yong-Ho;Lee Yong-Soon;Kang Kyung-Sun
    • Toxicological Research
    • /
    • v.21 no.2
    • /
    • pp.107-113
    • /
    • 2005
  • [ $BARODON^{(R)}$ ] is a multi-purpose, high functional alkali solution made by mixing and liquid-ionizing silicon, calcium, sodium, borax, organic carbon chemicals and silver. In this study, we have investigated the apoptotic potential and mechanistic insights of $BARODON^{(R)}$ in human gastric cancer cell line (AGS cells). In MTT assay, $BARODON^{(R)}$ reduced cell viability in AGS cells. Morphological features of apoptosis with marked cytoplasmic vacuolation and appearance of apoptotic peaks in flow cytometry were observed in AGS cells with$BARODON^{(R)}$ treatment. In addition, $BARODON^{(R)}$ induced apoptosis of stomach cancer cell is related to bax up-regulation, caspase 7 protease activation and subsequent cleavage of poly (ADP-ribose) polymerase (PARP). These results suggest that BARODON can induce the apoptosis of AGS cells through modulation of bcl-2 family and the activation of intrinsic caspase cascades, indicating that it is potentially useful as a anti-cancer agent.

Properties of Portland Cement Clinker Using Polysilicon Sludge (폴리실리콘 슬러지를 원료로 사용한 포틀랜드 시멘트 클링커의 특성)

  • Lee, Seung-Heun;Lee, Se-Jin;Woo, Yang-Yee;Park, Jeoung-Soo
    • Journal of the Korean Recycled Construction Resources Institute
    • /
    • v.2 no.4
    • /
    • pp.328-334
    • /
    • 2014
  • This study reviewed the usability of sludge, a material that is additionally created when polysilicon (a solar light material) is produced, as the raw material for cement clinker. It was evaluated that when cement clinker is produced, the chloric component of polysilicon acted as a mineralizer in the firing process. In addition, the physical features of the produced cement were measured. The setting time of the produced cement was reduced as the amount of content of polysilicon sludge increased. Such results were drawn because the chloric component acted as hydration accelerator and enhanced the dissolution of calcium hydroxide that was formed by hydration of $C_3S$. Furthermore, for such reason, on the day 1, the compression strength of mortar increased as the content of polysilicon sludge increased. In day 3, 7, and 28, the tendency in which the compression strength increasing up to 5% of the amount of added polysilicon sludge was shown. It is because when clinker was produced, the chloric component increased the amount of $C_3S$ mineral created, thus enhancing the compression strength after day 3.

Laser crystallization in active-matrix display backplane manufacturing

  • Turk, Brandon A.;Herbst, Ludolf;Simon, Frank;Fechner, Burkhard;Paetzel, Rainer
    • 한국정보디스플레이학회:학술대회논문집
    • /
    • 2008.10a
    • /
    • pp.1261-1262
    • /
    • 2008
  • Laser-based crystallization techniques are ideally-suited for forming high-quality crystalline Si films on active-matrix display backplanes, because the highly-localized energy deposition allows for transformation of the as-deposited a-Si without damaging high-temperature-intolerant glass and plastic substrates. However, certain significant and non-trivial attributes must be satisfied for a particular method and implementation to be considered manufacturing-worthy. The crystallization process step must yield a Si microstructure that permits fabrication of thin-film transistors with sufficient uniformity and performance for the intended application and, the realization and implementation of the method must meet specific requirements of viability, robustness and economy in order to be accepted in mass production environments. In recent years, Low Temperature Polycrystalline Silicon (LTPS) has demonstrated its advantages through successful implementation in the application spaces that include highly-integrated active-matrix liquid-crystal displays (AMLCDs), cost competitive AMLCDs, and most recently, active-matrix organic light-emitting diode displays (AMOLEDs). In the mobile display market segment, LTPS continues to gain market share, as consumers demand mobile devices with higher display performance, longer battery life and reduced form factor. LTPS-based mobile displays have clearly demonstrated significant advantages in this regard. While the benefits of LTPS for mobile phones are well recognized, other mobile electronic applications such as portable multimedia players, tablet computers, ultra-mobile personal computers and notebook computers also stand to benefit from the performance and potential cost advantages offered by LTPS. Recently, significant efforts have been made to enable robust and cost-effective LTPS backplane manufacturing for AMOLED displays. The majority of the technical focus has been placed on ensuring the formation of extremely uniform poly-Si films. Although current commercially available AMOLED displays are aimed primarily at mobile applications, it is expected that continued development of the technology will soon lead to larger display sizes. Since LTPS backplanes are essentially required for AMOLED displays, LTPS manufacturing technology must be ready to scale the high degree of uniformity beyond the small and medium displays sizes. It is imperative for the manufacturers of LTPS crystallization equipment to ensure that the widespread adoption of the technology is not hindered by limitations of performance, uniformity or display size. In our presentation, we plan to present the state of the art in light sources and beam delivery systems used in high-volume manufacturing laser crystallization equipment. We will show that excimer-laser-based crystallization technologies are currently meeting the stringent requirements of AMOLED display fabrication, and are well positioned to meet the future demands for manufacturing these displays as well.

  • PDF

Low Temperature Hermetic Packaging by Localized Heating using Forced Potential Scheme Micro Heater (Forced Potential Scheme 미세 가열기를 이용한 부분 가열 저온 Hermetic 패키징)

  • 심영대;신규호;좌성훈;김용준
    • Journal of the Microelectronics and Packaging Society
    • /
    • v.10 no.2
    • /
    • pp.1-5
    • /
    • 2003
  • In this project, the efficiency of localized heating for micro systems packaging is developed by using a forced potential scheme microheater. Less than 0.2 Mpa contact pressure was used for bonding with a 200 mA current input for $50{\mu}m$ width, $2{\mu}m$ height and $8mm{\times}8mm$, $5mm{\times}5mm$, $3mm{\times}3mm$ sized phosphorus-doped poly-silicon microheater. The temperature can be raised at the bonding region to $800^{\circ}C$, and it was enough to achieve a strong and reliable bonding in 3 minutes. The IR camera test results show improved uniformity in heat distribution compared with conventional microheaters. For performing the gross leak check, IPA (Isopropanol Alcohol) was used. Since IPA has better wetability than water, it can easily penetrate small openings, and is more suitable for conducting a gross leak check. The pass ratio of bonded dies was 67%, for conventional localized heating, and 85% for our newly developed FP scheme. The bonding strength was more than 25Mpa for FP scheme packaging, which shows that FP scheme can be a good candidate for micro-scale hermetic packaging.

  • PDF

Study on the Low-temperature process of zinc oxide thin-film transistors with $SiN_x$/Polymer bilayer gate dielectrics ($SiN_x$/고분자 이중층 게이트 유전체를 가진 Zinc 산화물 박막 트랜지스터의 저온 공정에 관한 연구)

  • Lee, Ho-Won;Yang, Jin-Woo;Hyung, Gun-Woo;Park, Jae-Hoon;Koo, Ja-Ryong;Cho, Eou-Sik;Kwon, Sang-Jik;Kim, Woo-Young;Kim, Young-Kwan
    • Journal of the Korean Applied Science and Technology
    • /
    • v.27 no.2
    • /
    • pp.137-143
    • /
    • 2010
  • Oxide semiconductors Thin-film transistors are an exemplified one owing to its excellent ambient stability and optical transparency. In particular zinc oxide (ZnO) has been reported because It has stability in air, a high electron mobility, transparency and low light sensitivity, compared to any other materials. For this reasons, ZnO TFTs have been studied actively. Furthermore, we expected that would be satisfy the demands of flexible display in new generation. In order to do that, ZnO TFTs must be fabricated that flexible substrate can sustain operating temperature. So, In this paper we have studied low-temperature process of zinc oxide(ZnO) thin-film transistors (TFTs) based on silicon nitride ($SiN_x$)/cross-linked poly-vinylphenol (C-PVP) as gate dielectric. TFTs based on oxide fabricated by Low-temperature process were similar to electrical characteristics in comparison to conventional TFTs. These results were in comparison to device with $SiN_x$/low-temperature C-PVP or $SiN_x$/conventional C-PVP. The ZnO TFTs fabricated by low-temperature process exhibited a field-effect mobility of $0.205\;cm^2/Vs$, a thresholdvoltage of 13.56 V and an on/off ratio of $5.73{\times}10^6$. As a result, We applied experimental for flexible PET substrate and showed that can be used to ZnO TFTs for flexible application.

Reduction of the residual stress of various oxide films for MEMS structure fabrication (MEMS 공정을 위한 여러 종류의 산화막의 잔류응력 제거 공정)

  • Yi, Sang-Woo;Kim, Sung-Un;Lee, Sang-Woo;Kim, Jong-Pal;Park, Sang-Jun;Lee, Sang-Chul;Cho, Dong-Il
    • Journal of Sensor Science and Technology
    • /
    • v.8 no.3
    • /
    • pp.265-273
    • /
    • 1999
  • Various oxide films are commonly used as a sacrificial layer or etch mask in the fabrication of microelectromechanical systems (MEMS). Large residual strain of these oxide films causes the wafer to bow, which can have detrimental effects on photolithography and other ensuing processes. This paper investigates the residual strain of tetraethoxysilane (TEOS), low temperature oxide (LTO), 7 wt% and 10 wt% phosphosilicate glass (PSG). Euler beams and a bent-beam strain sensor are used to measure the residual strain. A poly silicon layer is used as the sacrificial layer, which is selectively etched away by $XeF_2$. First, the residual strain of as-deposited films is measured, which is quite large. The residual strain of the films is also measured after annealing them not only at $500^{\circ}C$, $600^{\circ}C$, $700^{\circ}$ and $800^{\circ}C$ in $N_2$ environment for 1 hour but also at the conditions for depositing a $2\;{\mu}m$ thick polysilicon at $585^{\circ}C$ and $625^{\circ}C$. Our results show that the 7 wt% PSG is best suited as the sacrificial layer for $2\;{\mu}$ thick polysilicon processes.

  • PDF