• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2003.07b
• /
• pp.830-833
• /
• 2003

This paper describes the fabrication and characteristics of 3C-SiCOI sotctures by SDB and etch-back technology for high-temperature MEMS applications. In this work, insulator layers were formed on a heteroepitaxial 3C-SiC film grown on a Si(001) wafer by thermal wet oxidation and PECVD process, successively. The pre-bonding of two polished PECVD oxide layers made the surface activation in HF and bonded under applied pressure. The wafer bonding characteristics were evaluated by the effect of HF concentration used in the surface treatment on the roughness of the oxide and pre-bonding strength. Hydrophilic character of the oxidized 3C-SiC film surface was investigated by ATR-FTIR. The strength of the bond was measured by tensile strengthmeter. The bonded interface was also analyzed by SEM. The properties of fabricated 3C-SiCOI structures using etch-back technology in TMAH solution were analyzed by XRD and SEM. These results indicate that the 3C-SiCOI structure will offers significant advantages in the high-temperature MEMS applications.

• Transactions on Electrical and Electronic Materials
• /
• v.8 no.1
• /
• pp.26-31
• /
• 2007

The goal of this study is to determine if High Pressure Micro Jet (HPMJ) conditioning can be used as a substitute for, or in conjunction with, conventional diamond pad conditioning. Five conditioning methods were studied during which 50 ILD wafers were polished successively in a 100-mm scaled polisher and removal rate (RR), coefficient of friction (COF), pad flattening ratio (PFR) and scanning electron microscopy (SEM) measurements were obtained. Results indicated that PFR increased rapidly, and COF and removal rate decreased significantly, when conditioning was not employed. With diamond conditioning, both removal rate and COF were stable from wafer to wafer, and low PFR values were observed. SEM images indicated that clean grooves could be achieved by HPMJ pad conditioning, suggesting that HPMJ may have the potential to reduce micro scratches and defects caused by slurry abrasive particle residues inside grooves. Regardless of different pad conditioning methods, a linear correlation was observed between temperature, COF and removal rate, while an inverse relationship was seen between COF and PFR.

• Transactions of the Society of Information Storage Systems
• /
• v.1 no.2
• /
• pp.182-187
• /
• 2005

A large area micro mirror is an optical element that functions as changing an optical path by reflection in integrated optical system. We fabricated the large area silicon mirror by anisotropic etching using MEMS for implementation of integrated optical pickup. In this work, we report the optimum conditions to better fabricate and design, greatly improve mirror surface quality. To obtain mirror surface of $45^{\circ},\;9.74^{\circ}$ off-axis silicon wafer from (100) plane was used in etching condition of $80^{\circ}C$ with 40wt.% KOH solution. After wet etching, polishing process by MR fluid was applied to mirror surface for reduction of roughness. In the next step, after polymer coating on the polished Si wafer, the Si mirror was fabricated by UV curing using a trapezoid bar-type way structure. Finally, we obtained peak to valley roughness about 50 nm in large area of $mm^2$ and it is applicable to optical pickup using blu-ray wavelength as well as infrared wavelength.

• Transactions on Electrical and Electronic Materials
• /
• v.7 no.4
• /
• pp.163-166
• /
• 2006

The dishing and the erosion were evaluated on the tungsten CMP process with conventional and new developed slurry. The tungsten thin film was polished by orbital polishing equipment. Commercial pattern wafer was used for the evaluation. Both slurries were pre tested on the oxide region on the wafer surface and the removal rate was not different very much. At the pattern density examination, the erosion performance was increased at all processing condition due to the reduction of thickness loss in new slurry. However, the dishing thickness was not remarkably changed at high pattern density despite of the improvement at low pattern density. At the large pad area, the reduction of dishing thickness was clearly found at new tungsten slurry.

• Journal of Welding and Joining
• /
• v.24 no.2
• /
• pp.64-70
• /
• 2006

The 3-dimensional (3D) chip stacking technology is a leading technology to realize a high density and high performance system in package (SiP). There are several kinds of methods for chip stacking, but the stacking and interconnection through Cu filled through-hole via is considered to be one of the most advanced stacking technologies. Therefore, we studied the optimum process of through-hole via formation and Cu filling process for Si wafer stacking. Through-hole via was formed with DRIE (Deep Reactive ion Etching) and Cu filling was realized with the electroplating method. The optimized conditions for the via formation were RE coil power of 200 W, etch/passivation cycle time of 6.5 : 6 s and SF6 : C4F8 gas flow rate of 260 : 100 sccm. The reverse pulsed current of 1.5 A/dm2 was the most favorable condition for the Cu electroplating in the via. The Cu filled Si wafer was chemically and mechanically polished (CMP) for the following flip chip bumping technology.

• Journal of the Korean Crystal Growth and Crystal Technology
• /
• v.10 no.1
• /
• pp.42-47
• /
• 2000

The surface structure and the crystalline features in the near surface region have been investigated for CZ(Czochralski) grown Si wafers. Si wafers were annealed by RTA (Rapid Thermal Annealing) method in H$_2$ambient after mirror polished process. The densities of COPs (Crystal Originated Particles) after RTA process were remarkably decreased at the surface and in the region of 5um depth from the surface as well. terrace type surface structure which was formed by etching and re-arrangement of Si atoms during $H_2$annealing process also has been observed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.06a
• /
• pp.537-537
• /
• 2008

Copper (Cu) has been widely used for interconnection structure in intergrated circuits because of its properties such as a low resistance and high resistance to electromigration compared with aluminuim. Damascene processing for the interconnection structure utilizes 2-steps chemical mechanical polishing(CMP). After polishing, the removal of abrasive particles on the surfaces becomes as important as the polishing process. In the paper, buffing process for the removal of colloidal silica from polished Cu wafer was proposed and demonstrated.

• Korean Journal of Materials Research
• /
• v.15 no.12
• /
• pp.818-823
• /
• 2005

Sub-micron colloidal silica particles coated with nano-sized ceria were prepared by mixing of its silica and cerium salts hydrolysis, and modified by hydrothermal reaction. By using the slurries with and without hydrothermal modification containing above particles, oxide film coated on silicon wafer was polished. The modified slurries had higher polish rate due to increase of ceria fraction to silica through hydrothermal reaction. They revealed higher stability in wide range of pH $2\~10$ than ceria coated silica slurries without its modification.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2005.11a
• /
• pp.68-69
• /
• 2005

BTO ($BaTiO_3$) thin film is one of the high dielectric materials for high-density dynamic random access memories (DRAMs) due to its relatively high dielectric constant. It is generally known that BTO film is difficult to be etched by plasma etching, but high etch rate with good selectivity to pattern mask was required. The problem of sidewall angle also still remained to be solved in plasma etching of BTO thin film. In this study, we first examined the patterning possibility of BTO film by chemical mechanical polishing (CMP) process instead of plasma etching. The sputtered BTO film on TEOS film as a stopper layer was polished by CMP process with the self-developed $BaTiO_3$- and $TiO_2$-mixed abrasives slurries (MAS), respectively. The removal rate of BTO thin film using the$ BaTiO_3$-mixed abrasive slurry ($BaTiO_3$-MAS) was higher than that using the $TiO_2$-mixed abrasive slurry ($TiO_2$-MAS) in the same concentrations. The maximum removal rate of BTO thin film was 848 nm/min with an addition of $BaTiO_3$ abrasive at the concentration of 3 wt%. The sufficient within-wafer non-uniformity (WIWNU%)below 5% was obtained in each abrasive at all concentrations. The surface morphology of polished BTO thin film was investigated by atomic force microscopy (AFM).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.06a
• /
• pp.99-99
• /
• 2008

To grow the large diameter GaN with high structure and optical quality has been obtained by hydride vapor phase epitaxy(HVPE) method. In addition to the nitridation of $Al_2O_3$ substrate, we also developed a "step-growth process" to reduce or to eliminate the bowing of the GaN substrate caused by thermal mismatch during cool down after growth. The as-grown 380um thickness and 75mm diameter GaN layer was separated from the sapphire substrate by laser-induced lift-off process at $600^{\circ}C$. A problem with the free-standing wafer is the typically large bowing of such a wafer, due to the built in the defect concentration near GaN-sapphire interface. A polished G-surface of the GaN substrate were characterized by room temperature Double crystal X-ray diffraction (DCXRD), photoluminescence(PL) measurement, giving rise to the full-width at half maximum(FWHM) of the rocking curve of about 107 arcsec and dislocation density of $6.2\times10^6/cm^2$.