• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.10a
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• pp.939-942
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• 1997

In chemical mechanical polishing(CMP) there are many factors affecting the results. Temperature is one of the factors and it affects the removal rate. That is, the higher it arise, the more the material is removed. But the detailed temperature behavior is not discovered. In this study, we discover the distribution of temperature across the pad where the wafer has just been polished. And then we reveal the cause of the result in connection with the mechanical structure. In addition, we also discover the relationship of the friction force and normal force. With the result of two forces, we get the friction coefficient and obtain the contact model of the wafer and pad.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.11 no.5
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• pp.218-223
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• 2001

The chemical-mechanical polishing process was carried out for 2"-dia. sapphire wafer grown by horizontalBridgman method on the urethane lapping pad with the silica sol. The polished wafer shows the full-width at halfmaximum of 200~400 arcsec in double-crystal X-ray diffraction, indicating that the slicing, grinding and lapping processes before the polishing process affected the crystalline structural property of the wafer surface by the mechanical residual stress. For the inclusion of surface treatments after chemical-mechanical polishing such as the thermal annealing at the temperature of $1,200^{\circ}C$for 4 hrs. and chemical etching, the crystalline quality was sigdicantly enhanced with the reduced full-width at half maximum up to 8.3 arcsec.arcsec.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.8
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• pp.700-704
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• 2003

This paper describes on characteristics of 2" 3C-SiC wafer bonding using PECVD (plasma enhanced chemical vapor deposition) oxide and HF (hydrofluoride acid) for SiCOI (SiC-on-Insulator) structures and MEMS (micro-electro-mechanical system) applications. In this work, insulator layers were formed on a heteroepitaxial 3C-SiC film grown on a Si (001) wafer by thermal wet oxidation and PECVD process, successively. The pre-bonding of two polished PECVD oxide layers made the surface activation in HF and bonded under applied pressure. The bonding characteristics were evaluated by the effect of HF concentration used in the surface treatment on the roughness of the oxide and pre-bonding strength. Hydrophilic character of the oxidized 3C-SiC film surface was investigated by ATR-FTIR (attenuated total reflection Fourier transformed infrared spectroscopy). The root-mean-square suface roughness of the oxidized SiC layers was measured by AFM (atomic force microscope). The strength of the bond was measured by tensile strength meter. The bonded interface was also analyzed by IR camera and SEM (scanning electron microscope), and there are no bubbles or cavities in the bonding interface. The bonding strength initially increases with increasing HF concentration and reaches the maximum value at 2.0 ％ and then decreases. These results indicate that the 3C-SiC wafer direct bonding technique will offers significant advantages in the harsh MEMS applications.ions.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.7 no.3
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• pp.393-399
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• 1997

H-SiC single crystals were successfully grown by the sublimation method and the optimum growth conditions were established. The grown SiC crystals were about 33 mm in diameter and 11 mm in length. The micropipe density of the polished SiC wafers was 400/$\textrm{cm}^2$, and the planar defect density was 50/$\textrm{cm}^2$. Raman spectroscopy and DCXRD analysis were used to examine the crystallinity of Acheson seeds and the 6H-SiC wafers. As a result, the crystallinity of the 6H-SiC wafers was better than that of Acheson seeds. For examination of the electrical properties of the undopped 6H-SiC wafers Hall measurements were applied. According to the measurements the carrier concentration was estimated to be $3.91{\times}10^{15}/\textrm {cm}^3$ and doping type of the undopped. 6H-SiC wafers was n-type.

• Korean Journal of Materials Research
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• v.18 no.6
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• pp.307-312
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• 2008

In this study, a new cleaning process with a low cost of ownership (CoO) was developed with ozonated DI water ($DIO_3$). An ozone concentration of 40 ppm at room temperature was used to remove organic wax film and particles. Wax residues thicker than $200\;{\AA}$ remained after only a commercial dewaxer treatment. A $DIO_3$ treatment in place of a dewaxer showed a low removal rate on a thick wax layer of $8000\;{\AA}$ due to the diffusion-limited reaction of ozone. A dewaxer was combined with a $DIO_3$ rinse to reduce the wax removal time and remove wax residue completely. Replacing DI rinse with the $DIO_3$ rinse resulted in a surface with a contact angle of less than $5^{\circ}$, which indicates no further cleaning steps would be required. The particle removal efficiency (PRE) was further improved by combining a SC-1 cleaning step with the $DIO_3$ rinsing process. A reduction in the process time was obtained by introducing $DIO_3$ cleaning with a dewaxing process.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.6
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• pp.291-296
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• 2006

In this study, the sputtered BTO film was polished by CMP process with the self-developed $BaTiO_3$- and $TiO_2$-mixed abrasives slurries (MAS), respectively. The removal rate of BTO ($BaTiO_3$) thin film using the $BaTiO_3$-mixed abrasive slurry (BTO-MAS) was higher than that using the $TiO_2$-mixed abrasives slurry ($TiO_2$-MAS) in the same concentrations. The maximum removal rate of BTO thin film was 848 nm/min with an addition of $BaTiO_3$ abrasive at the concentration of 3 wt%. The sufficient within-wafer non-uniformity (WIWNU%) below 5% was obtained in each abrsive at all concentrations. The surface morphology of polished BTO thin film was investigated by atomic force microscopy (AFM).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.2
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• pp.131-136
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• 2000

We have investigated the slurry induced metallic contaminations of undoped and doped silicate oxides surface on CMP cleaning process. The metallic contaminations by CMP slurry were evaluated in four different oxide films, such as plasma enhanced tetra-ethyl-orthyo-silicate glass(PE-TEOS), O3 boro-phos-pho-silicate glass(O3-BPSG), PE-BPSG, and phospho-silicate glass(PSG). All films were polished with KOH-based slurry prior to entering the post-CMP cleaner. The Total X-Ray fluorescence(TXRF) measurements showed that all oxide surfaces are heavily contaminated by potassium and calcium during polishing which is due to a CMP slurry. The polished O3-BPSG films presented higher potassium and calcium contaminations compared to PE-TEOS because of a mobile ions gettering ability of phosphorus. For PSG oxides, the slurry induced mobile ion contamination increased with an increase of phosphorus contents. In addition, the polishing removal rate of PSG oxides had a linear relationship as a function of phosphorus contents.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.47-48
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• 2007

A CMP Process has many factors that affect result of a polished wafer. Dominant factors are velocity, pressure and temperature in process. A pad profile is also considered as affecting factor of CMP. Accoding to variation of a pad profile, the each pan of a wafer is differently pressured. It appears to affect the uniformity of a wafer. A pad profile varies as a swing arm conditioner which have been ordinarily used in industry. A swing arm conditioner has several sectors in its swing path. This study aims that a wafer get a good uniformity as swing arm conditioner's path on pad is analyzed and simulated. Through the simulation, tendency of pad profile after conditioning will be predicted and the result of simulation compared with the result of experiment. The optimized pad profile would be made by to vary swing arm's velocity on each sector. In order to maintain the optimized profile, conditioner design or swing arm's velocity should be changed and designed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.05b
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• pp.30-33
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• 2001

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectrics, which can apply to employed in integrated circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of free-defects in inter-level dielectrics (ILD). Especially, defects like micro-scratch lead to severe circuit failure, and affects yield. CMP slurries can contain particles exceeding $1{\mu}m$ size, which could cause micro-scratch on the wafer surface. The large particles in these slurries may be caused by particle agglomeration in slurry supply line. To reduce these defects, slurry filtration method has been recommended in oxide CMP. In this work, we have studied the effects of filtration and the defect trend as a function of polished wafer count using various filters in inter-metal dielectric(IMD)-CMP. The filter installation in CMP polisher could reduce defect after IMD-CMP. As a result of micro-scratches formation, it shows that slurry filter plays an important role in determining consumable pad lifetime.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.7
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• pp.557-561
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• 2001

Chemical mechanical polishing (CMP) process has been widely used to planarize dielectric layers, which can be applied to the integraded circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of in the defect-free inter-level dielectrics (ILD). Especially, defects such as micro-scratch lead to severe circuit failure which affect yield. CMP slurries can contain particles exceeding 1㎛ in size, which could cause micro-scratch on the wafer surface. The large particles in these slurries may be caused by particles agglomeration in slurry supply line. To reduce these defects, slurry filtration method has been recommended in oxide CMP. In this work, we have studied the effects of filtration and the defect trend as a function of polished wafer count using various filters in inter-metal dielectrics(IMD)-CMP process. The filter installation in CMP polisher could reduce defects after IMD-CMP process. As a result of micro-scratch formation, it is shown that slurry filter plays an important role in determining consumable pad lifetime. The filter lifetime is dominated by the defects. We have concluded that slurry filter lifetime is fixed by the degree of generating defects.