• 한국정밀공학회지
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• 제34권2호
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• pp.107-114
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• 2017

In this investigation, we describe a metrological technique for surface and thickness profiles of a silicon (Si) wafer by using a 6 degree of freedom (DOF) stitching method. Low coherence scanning interferometry employing near infrared light, partially transparent to a Si wafer, is adopted to simultaneously measure the surface and thickness profiles of the wafer. For the large field of view, a stitching method of the sub-aperture measurement is added to the measurement system; also, 6 DOF parameters, including the lateral positioning errors and the rotational error, are considered. In the experiment, surface profiles of a double-sided polished wafer with a 100 mm diameter were measured with the sub-aperture of an 18 mm diameter at $10\times10$ locations and the surface profiles of both sides were stitched with the sub-aperture maps. As a result, the nominal thickness of the wafer was $483.2{\mu}m$ and the calculated PV values of both surfaces were $16.57{\mu}m$ and $17.12{\mu}m$, respectively.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.323-323
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• 2010

Saw damage of crystalline silicon wafer is unavoidable factor. Usually, alkali treatment for removing the damage has been carried out as the saw damage removal (SDR) process for priming the alkali texture. It usually takes lots of time and energy to remove the sawed damages for solar grade crystalline silicon wafers We implemented two different mixed acidic solution treatments to obtain the improved surface structure of silicon wafer without much sacrifice of the silicon wafer thickness. At the first step, the silicon wafer was dipped into the mixed acidic solution of $HF:HNO_3$=1:2 ration for polished surface and at the second step, it was dipped into the diluted mixed acidic solution of $HF:HNO_3:H_2O$=7:3:10 ratio for porous structure. This double treatment to the silicon wafer brought lower reflectance (25% to 6%) and longer carrier lifetime ($0.15\;{\mu}s$ to $0.39\;{\mu}s$) comparing to the bare poly-crystalline silicon wafer. With optimizing the concentration ratio and the dilution ratio, we can not only effectively substitute the time consuming process of SDR to some extent but also skip plasma enhanced chemical vapor deposition (PECVD) process. Moreover, to conduct alkali texture for pyramidal structure on silicon wafer surface, we can use only nitric acid rich solution of the mixed acidic solution treatment instead of implementing SDR.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2007년도 춘계학술대회 논문집
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• pp.755-756
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• 2007

• 한국기계가공학회지
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• 제11권2호
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• pp.144-151
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• 2012

Polishing is not only one of the most frequently adopted processes in modern industries, but also the most critical one to the surface quality of the products such as semi conductor wafers and LED sapphire wafers. With the required specifications for the wafer surface quality getting more and more strengthened, the manufacturers are spending huge amount of cost to renew the machine to meet the enhanced surface specifications. Surface qualities of the wafers are mostly damaged by the structural vibrations of the polishing machines. In this paper, the dynamic characteristics of a wafer polishing machine have been analyzed through the frequency response test and the computer simulation. And the supporting structure of a polishing machine has been investigated to minimize the vibration transmissions, to improve the stability of the machine and further to reduce the defects of the polished products. The result of the study shows that simple design modifications of the supporting structure without altering the main structure of the machine can substantially suppress the vibrations of the machine with negligible expenses.

• Transactions on Electrical and Electronic Materials
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• 제12권2호
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• pp.56-59
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• 2011

The characterization of the chemical mechanical polishing (CMP) process for undensified phophosilicate glass (PSG) film is reported using design of experiments (DOE). DOE has been used by experimenters to understand the relationship between the input variables and responses of interest in a simple and efficient way, and it typically is beneficial for determining the appropriatesize of experiments with multiple process variables and making statistical inferences for the responses of interest. The equipment controllable parameters used to operate the machine consist of the down force of the wafer carrier, pressure on the back side wafer, table and spindle speeds (SS), slurry flow (SF) rate, pad condition, etc. None of these are independent ofeach other and, thus, the interaction between the parameters also needs to be understoodfor improved process characterization in CMP. In this study, we selected the five controllable equipment parameters the most recommendedby process engineers, viz. the down force (DF), back pressure (BP), table speed (TS), SS, and SF, for the characterization of the CMP process with respect to the material removal rate and film uniformity in percentage terms. The polished material is undensified PSG which is widely used for the plananization of multi-layered metal interconnects. By statistical modeling and the analysis of the metrology data acquired from a series of $2^{5-1}$ fractional factorial designs with two center points, we showed that the DF, BP and TS have the greatest effect on both the removal rate and film uniformity, as expected. It is revealed that the film uniformity of the polished PSG film contains two and three-way interactions. Therefore, one can easily infer that process control based on a better understanding of the process is the key to success in current semiconductor manufacturing, in which the size of the wafer is approaching 300 mm and is scheduled to continuously increase up to 450 mm in or slightly after 2012.

• Transactions on Electrical and Electronic Materials
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• 제12권3호
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• pp.115-118
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• 2011

Process characterization of the chemical mechanical polishing (CMP) process for undensified phosphosilicate glass (PSG) film is reported using design of experiments (DOE). DOE has been addressed to experimenters to understand the relationship between input variables and responses of interest in a simple and efficient way. It is typically beneficial for determining the adequate size of experiments with multiple process variables and making statistical inferences for the responses of interests. Equipment controllable parameters to operate the machine include the down force (DF) of the wafer carrier, pressure on the backside of the wafer, table and spindle speed (SS), slurry flow rate, and pad condition. None of them is independent; thus, the interaction between parameters also needs to be indicated to improve process characterization in CMP. In this paper, we have selected the five controllable equipment parameters, such as DF, back pressure (BP), table speed (TS), SS, and slurry flow (SF), most process engineers recommend to characterize the CMP process with respect to material removal rate (RR) and film uniformity as a percentage. The polished material is undensified PSG. PSG is widely used for the plananization in multi-layered metal interconnects. We identify the main effect of DF, BP, and TS on both RR and film uniformity, as expected, by the statistical modeling and analysis on the metrology data acquired from a series of $2^{5-1}$ fractional factorial design with two center points. This revealed the film uniformity of the polished PSG film contains two and three-way interactions. Therefore, one can easily infer that the process control based on better understanding of the process is the key to success in semiconductor manufacturing, typically when the wafer size reaches 300 mm and is continuously scheduled to expand up to 450 mm in or little after 2012.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.161-161
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• 2008

The oxide film of silicon wafer has been mainly polished by fumed silica, colloidal silica or ceria slurry. Because colloidal silica slurry is uniform and highly dispersed composed of spherical shape particles, by which the oxide film polished remains to be less scratched in finishing polishing process. Even though the uniformity and spherical shape is advantage for reducing the scratch, it may also be the factor to decrease the removal rate. We have studied the correlation of silica abrasive particles and CMP characteristics by varying pH, down force, and table rotation rate in polishing. It was found that the CMP polishing is dependent on the morphology, aggregation, and the surface property of the silica particles.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 Techno-Fair 및 추계학술대회 논문집 전기물성,응용부문
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• pp.148-149
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• 2007

We present the design and fabrication prcoess of a two-axis tilting micromirror device driven by the electrostatic vertical comb actuator. A high aspect-ratio comb actuator is fabricated by multiple DRIE process in order to achieve large scan angle. The proposed fabrication process enables a mirror to be fabricated on the wafer-scale. By bonding a double-side polished (DSP) wafer and a silicon-on-insulator (SOI) wafer together, all actuators on the wafer are completely hidden under the reflectors. Nickel lines are embedded on a Pyrex wafer for the electrical access to numerous electrodes of mirrors. An anodic bonding step is implemented to contact electrical lines with ail electrodes on the wafer at a time. The mechanical angle of a fabricated mirror has been measured to be 1.9 degree and 1.6 degree, respectively, in the two orthogonal axes under driving voltages of 100 V. Also, a $8{\times}8$ array of micromirrors with high fill-factor of 70 % is fabricated by the same fabrication process.

• 한국정밀공학회지
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• 제19권5호
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• pp.149-158
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• 2002

Recently, the minimum line width shows a tendency to decrease and the multi-level increases in semiconductor. Therefore, a planarization technique is needed and chemical mechanical polishing(CMP) is considered as one of the most suitable process. CMP accomplishes a high polishing performance and a global planarization of high quality. However there are several defects in CMF, such as micro-scratches, abrasive contaminations and non-uniformity of polished wafer edges. Wet etching process including spin-etching can eliminate the defects of CMP. It uses abrasive-free chemical solution instead of slurry. On this study, ILD(Interlayer-Dielectric) was removed by CMP and wet etching process using DHF(Diluted HF) in order to investigate the possibility of planrization by wet etching mechanism. In the thin film wafer, the results were evaluated from the viewpoint of material removal rate(MRR) and within wafer non-uniformity(WIWNU). And the pattern step heights were also compared for the purpose of planarity characterization of the patterned wafer. Moreover, Chemical polishing process which is the wet etching process with mechanical energy was introduced and evaluated for examining the characteristics of planarization.

• 열처리공학회지
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• 제26권4호
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• pp.178-184
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• 2013

The effects of thickness and surface grinding condition on the fracture strength of Si wafer with a thickness under $100{\mu}m$ were investigated. Fracture strength was measured by ball breaker test for about 330 dies (size: $4mm{\times}4mm$) per each wafer. For statistical analysis of the fracture strength, scale factor was determined from Weibull plot. Ball breaker fracture strength was observed to increase with decreasing thickness of silicon die. For the silicon dies of different surface conditions, ball breaker fracture strength was high in the order of polished, ground (#4800), and ground (#320 grit) specimen. Probabilistic fracture strength (i.e., scale factor) increased with decreasing surface roughness of silicon die.