• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• 제16권5호
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• pp.365-371
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• 2003

We prepared silicon on insulator(SOI) wafer pairs of Si/1800${\AA}$ -SiO$_2$ ∥ 1800${\AA}$ -SiO$_2$/Si using water direct bonding method. Wafer pairs bonded at room-temperature were annealed by a normal furnace system or a fast linear annealing(FLA) equipment, and the micro-structure of bonding interfaces for each annealing method was investigated. Upper wafer of bonded pairs was polished to be 50 $\mu\textrm{m}$ by chemical mechanical polishing(CMP) process to confirm the real application. Defects and bonding area of bonded water pairs were observed by optical images. Electrical and mechanical properties were characterized by measuring leakage current for sweeping to 120 V, and by observing the change of wafer curvature with annealing process, respectively. FLA process was superior to normal furnace process in aspects of bonding area, I-V property, and stress generation.

• Proceedings of the Materials Research Society of Korea Conference
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• 한국재료학회 2002년도 춘계 학술발표강연 및 논문개요집
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• pp.134-134
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• 2002

• Proceedings of the Korean Society of Precision Engineering Conference
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• 한국정밀공학회 1997년도 춘계학술대회 논문집
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• pp.921-926
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• 1997

SOI(Silicon On lnsulator) technology is many advantages in the gabrication of MOS(Metal-Oxide Semiconductor) and CMOS(Complementary MOS) structures. These include high speed, lower dynamic power consumption,greater packing density, increased radiation tolearence et al. In smiple form of bonded SOL wafer manufacturing, creation of a bonded SOI structure involves oxidizing at least one of the mirror polished silicon surfaces, cleaning the oxidized surface and the surface of the layer to which it will be bonded,bringing the two cleanded surfaces together in close physical proximity, allowing the subsequent room temperature bonding to proceed to completion, and than following this room temperature joining with some form of heat treatment step,and device wafer is thinned to the target thickness. This paper has been performed to investigate the possibility of the bonded SOI wafer manufacturing Especially, we focused on the bonding quality and thinning method. Finally,we achieved the bonded SOI wafer that Si layer thickness is below 3 .mu. m and average roughness is below 5.angs.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 한국정밀공학회 2000년도 춘계학술대회 논문집
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• pp.854-857
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• 2000

Chemical Mechanical Polishing(CMP) has been accepted as one of the essential processes for VLSI fabrication. However, as the polishing process continues, pad pores get to be glazed by polishing residues, which hinder the supply of new slurry. This defect makes removal rate decrease with a number of polished wafer and the desired within-chip planarity, within wafer and wafer-to-wafer nonuniformity are unable to be achieved. So, pad conditioning is essential to overcome this defect. The eletroplated diamond grit disk is used as the conventional conditioner, And alumina long fiber, the .jet power of high pressure deionized water and vacuum compression are under investigation. But, these methods have the defects like scratches on wafer surface by out of diamond grits, subsidences of pad pores by over-conditioning, and the limits of conditioning effect. To improve these conditioning methods. this paper presents the Characteristics of Ultrasonic conditioning aided by cavitation.

• Journal of the Korean Crystal Growth and Crystal Technology
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• 제10권5호
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• pp.350-355
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• 2000

The fabrication of sapphire wafer in C plane has been developed by horizontal Bridgeman method and GaN based semiconductor epitaxial growth has been carried out in metal organic chemical vapour deposition. The single crystalline ingot of sapphire has been utilized for 2 inch sapphire wafers and wafer slicing and lapping machines were designed. These several steps of lapping processes provided the mirror-like surface of sapphire wafer. The measurements of the surface flatness and the roughness were carried out by the atomic force microscope. The GaN thin film growth on the developed wafer was confirmed the wafer quality and applicability to blue light emitting devices.

• Journal of the Korean Society of Manufacturing Process Engineers
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• 제19권3호
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• pp.22-28
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• 2020

This paper investigates the effects of retaining ring materials, particularly PPS and PEEK, used in the CMP process, on wafer polishing and ring wear. CMP can be performed using bonded type retaining rings made with PPS or injection molding type retaining rings made with PEEK. In this study, after polishing a wafer with a PPS retaining ring, the average profile height of the wafer was 0.098 ㎛ less than that of the wafer polished with a PEEK retaining ring, implying that PPS retaining rings achieve a higher polishing rate. In addition, the center area of the wafer profile had less deviation and improved flatness after polishing with the PPS ring. These results indicate that a higher polishing rate and smaller profile height deviation can be achieved using retaining rings made with PPS compared to retaining rings made with PEEK. Therefore, with semiconductor circuit patterns becoming finer and wafer sizes becoming larger, the use of PPS in CMP retaining rings can obtain more stable wafer polishing results compared to that of PEEK.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• 제22권2호
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• pp.310-317
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• 2013

In this paper, the contact pressure of the wafer and polishing pad for final polishing process for 300 mm-wafer were investigated through numerical analysis using FEM tool, ANSYS. The distribution of the contact pressure is one of main parameters which affects on the flatness and surface roughness of polished wafers. Two types of polishing head, a hard type head with ceramic disk and a soft type head with air bag were considered. The effects of the deformation and initial shape of table on the contact pressure were also examined. Both heads and tables were modeled as 3D finite element model from solid model, and the material properties of polishing pads and rubber plate for the air-bag head were obtained from tensile tests. The contact pressure deviation on wafer surface was smaller with air bag head than hard type head even when the table had form errors such as convex or concave. From this 3D analysis, it could be concluded that the air-bag head has better uniformity of the contact pressure on wafer. Also, the effects of inner diameter of air bag and radial clearance between wafer and retainer were investigated as view point of contact pressure concentration on the edge of wafer.

• International Journal of Precision Engineering and Manufacturing
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• 제9권2호
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• pp.8-10
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• 2008

Chemical mechanical polishing (CMP) is a very precise planarization technique where a wafer is polished by a slurry-coated pad. A slurry is dropped on the rotating pad surface and is supplied between the wafer and the pad. This research aims at reducing the slurry consumption and removing waste particles quickly from the wafer. To study the roles of grooves, slurry flows were simulated using the volume of fluid method (two-phase model for air and slurry) for pads with no grooves, and for pads with circular grooves.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제45권8호
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• pp.11-16
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• 2008

In this paper, firstly we made of the rapid thermal processor equipment with the specifically useful structure to measure wafer stress. Secondly we made of the laser interferometry to inspect the wafer surface curvature based on the large deformation theory. And then the wafer surface fringe image was obtained by experiment, and the full field stress distribution of wafer surface comes into view by signal processing with thining and pitch mapping. After wafer was ground by 1mm and polished from the back side to get easily deformation, and it was heated by three to four times thermal treatments at about 1000 degree temperature. Finally the severe deformation between wafer before and after the heat treatment was shown.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 한국전기전자재료학회 2002년도 춘계학술대회 논문집 유기절연재료 전자세라믹 방전플라즈마 일렉트렛트 및 응용기술
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• pp.223-227
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• 2002

As the channel length of device shrinks below $0.13{\mu}m$, CMP(chemical mechanical polishing) process got into key process for global planarization in the chip manufacturing process. The removal rate and non-uniformity of the CMP characteristics occupy an important position to CMP process control. Especially, the post-CMP thickness variation depends on the device yield as well as the stability of subsequent process. In this paper, every wafer polished two times for the improvement of oxide CMP process characteristics. Then, we discussed the removal rate and non-uniformity characteristics of post-CMP process. As a result of CMP experiment, we have obtained within-wafer non-uniformity (WIWNU) below 4 [%], and wafer-to-wafer non-uniformity (WTWNU) within 3.5 [%]. It is very good result, because the reliable non-uniformity of CMP process is within 5 [%].