• Proceedings of the KIEE Conference
• /
• 1999.07d
• /
• pp.1750-1752
• /
• 1999

An active-matrix liquid crystal display (LCD) using thin film transistors (TFTs) has been widely recognized as having potential for high-quality color flat-panel displays. Pixel-Design Array Simulation Tool (PDAST) was used to profoundly understand the gate signal distortion and pixel charging capability, which are the most critical limiting factors for high-quality TFT-LCDs. Since PDAST can simulate the sate, data and pixel voltages of a certain pixel on TFT array at any time and at any location on an array, the effect of the new set of capacitance models on the pixel operations can be effectively analyzed. The set of models which is adopted from VLSI interconnections calculate more precise capacitance. The information obtained from this study could be utilized to design the larger area and finer image quality panel.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2000.04a
• /
• pp.165-168
• /
• 2000

An active-matrix LCD using thin film transistors (TFT) has been widely recognized as having potential for high-quality color fiat-panel displays. Pixel-Design Array Simulation Tool (PDAST) was used to profoundly understand the gate signal distortion and pixel charging capability, which are the most critical limiting factors for high-quality TFT-LCDs. In addition, PDAST can estimate voltage distributions in common electrode which can affect pixel voltage and feed-through voltage. Since PDAST can simulate the gate, data and the pixel voltages of a certain pixel on TFT array at any time and at any location on an array, the effect of common electrode voltage can be effectively analyzed. The information obtained from this study could be utilized to design the larger area and finer image quality panel.

• Journal of Sensor Science and Technology
• /
• v.27 no.6
• /
• pp.357-361
• /
• 2018

This paper presents an averaging current adjustment technique for reducing the pixel resistance variation in a bolometer-type uncooled infrared image sensor. Each unit pixel was composed of an active pixel, a reference pixel for the averaging current adjustment technique, and a calibration circuit. The reference pixel was integrated with a polysilicon resistor using a standard complementary metal-oxide-semiconductor (CMOS) process, and the active pixel was applied from outside of the chip. The averaging current adjustment technique was designed by using the reference pixel. The entire circuit was implemented on a chip that was composed of a reference pixel array for the averaging current adjustment technique, a calibration circuit, and readout circuits. The proposed reference pixel array for the averaging current adjustment technique, calibration circuit, and readout circuit were designed and fabricated by a $0.35-{\mu}m$ standard CMOS process.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.48 no.6
• /
• pp.416-428
• /
• 1999

A user-interactive pixel design tool for high-quality TFT-LCDs is realized and used to explore the sensitivity of the various array and device parameters for optimizing pixel design. In this tool, the Thompson cable equation and gradual-channel approximation were used for the gate time delay and TFT current modeling respectively. With this tool, each capacitance element, and TFT and array dimensions can be optimized under given design specifications. The electrical characteristics such ascharging ratio, gate time delay, pixel voltage level-shift, and holding ratio can be analyzed. The sensitivity analysis of those design parameters were executed and presented.

• Journal of the Korea Society for Simulation
• /
• v.10 no.3
• /
• pp.59-70
• /
• 2001

Typical low-level image processing tasks require thousands of operations per pixel for each input image. Traditional general-purpose computers are not capable of performing such tasks in real time. Yet important features of traditional computers are not exploited by low-level image processing tasks. Since storage requirements are limited to a small number of low-precision integer values per pixel, large hierarchical memory systems are not necessary. The mismatch between the demands of low-level image processing tasks and the characteristics of conventional computers motivates investigation of alternative architectures. The structure of the tasks suggests employing an array of processing elements, one per pixel, sharing instructions issued by a single controller. In this paper we implemented various image processing filtering using the format converter. Also, we realized from conventional gray image process to color image process. This design method is based on realized the large processor-per-pixel array by integrated circuit technology This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware.

• Nuclear Engineering and Technology
• /
• v.52 no.11
• /
• pp.2572-2580
• /
• 2020

Emerging gamma ray detection applications that utilize neutron-based interrogation result in the prompt emission of high-energy (>2 MeV) gamma-rays. Rapid imaging is enabled by scintillators that possess high density, high atomic number, and excellent energy resolution. In this paper, we evaluate the bright (50,000 photons/MeV) oxide scintillator, cerium-doped Gd₂Al₂Ga₃O₁₂ (GAGG(Ce)). A silicon photomultiplier (SiPM) array is coupled to a GAGG(Ce) scintillator array (12 × 12 pixels) and integrated into a coded-aperture based gamma-ray imaging system. A resistor-based symmetric charge division circuit was used reduce the multiplicity of the analog outputs from 144 to 4. The developed system exhibits 9.1%, 8.3%, and 8.0% FWHM energy resolutions at 511 keV, 662 keV, and 1173.2 keV, respectively. In addition, a pixel-identification resolution of 602 ㎛ FWHM was obtained from the GAGG(Ce) scintillator array.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2008.10a
• /
• pp.352-354
• /
• 2008

A 15.4" WXGA TFT-LCD, featuring integrated a-Si:H gate driver circuits and reduced data driver ICs, has been developed. To reduce number of data lines into 1/2 of conventional structure, the pixel array has been re-mapped with re-organized data signal. Unintended artificial effects such as flicker were removed by adopting the novel pixel array having a 'zigzag' map. To minimize the power consumption, a column inversion method was incorporated in the zigzag pixel array (Fig.1) without modifying the polarity map of conventional dot inversion method.

• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.269-272
• /
• 2001

In this paper we proposed the format converter design and implementation for real time image processing. This design method is based on realized the large processor-per-pixel array by integrated circuit technology in which this two types of integrated structure is can be classify associative parallel processor and parallel process with DRAM cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilized the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start

• Proceedings of the KIEE Conference
• /
• 2003.11c
• /
• pp.777-780
• /
• 2003

We have tried to create a vision system like human eye for a long time. We have obtained some distinguished results through many studies. Stereo vision is the most similar to human eye among those. This is the process of recreating 3-D spatial information from a pair of 2-D images. In this paper, we have designed a stereo matching algorithm based on systolic array architecture using edges and pixel data. This is more advanced vision system that improves some problems of previous stereo vision systems. This decreases noise and improves matching rate using edges and pixel data and also improves processing speed using high integration one chip FPGA and compact modules. We can apply this to robot vision and automatic control vehicles and artificial satellites.

• Journal of Korea Multimedia Society
• /
• v.20 no.12
• /
• pp.2009-2015
• /
• 2017

A two-dimensional lens is required to reproduce both the horizontal and vertical parallax through an autostereoscopic 3D display. Among the two-dimensional lenses, a hexagonal micro lens array (MLA) having good optical efficiency is mainly used. However, the hexagonal MLA has complex geometric features. The first feature is that the lens cells are zigzagged in the vertical direction, which should be reflected in the view number calculation for each sub-pixel. The second feature is that the four sides of a hexagonal lens cell are tilted, requiring a more careful view index assignment to the lens cell. In this paper, we propose a sub-pixel multiplexing scheme suitable for the features of the hexagonal MLA. We also propose a view-overlay algorithm based on a two-dimensional lens and compare subjective image quality with existing view-selection through autostereoscopic 3D display implementation.