• Journal of the Korea Society of Computer and Information
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• v.7 no.3
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• pp.135-142
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• 2002

In this paper, we proposed the new structure of the Rake Finger using Walsh Switch, the shared accumulator and the pipeline FWHT algorithm for reducing the signal processing complexity resulting from the increase of the number of data correlators. The number of computational operation in the proposed data correlators is 160 additions when the number of walsh code channels is 4. As a result, it is reduced about 3.2 times other than the number of computational operation of the conventional ones. Also, the result shows that the data processing time of the proposed Rake Finger architecture is 90,496〔ns〕 and the conventional ones is 110,696〔ns〕. It is 18.3% faster than the data processing time of the conventional Rake Finger architecture.

• Journal of Convergence for Information Technology
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• v.9 no.8
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• pp.1-8
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• 2019

Dialog system is becoming a new dominant interaction way between human and computer. It allows people to be provided with various services through natural language. The dialog system has a common structure of a pipeline consisting of several modules (e.g., speech recognition, natural language understanding, and dialog management). In this paper, we tackle a task of domain classification for the natural language understanding module by employing machine learning models such as convolutional neural network and random forest. For our dataset of seven service domains, we showed that the random forest model achieved the best performance (F1 score 0.97). As a future work, we will keep finding a better approach for domain classification by investigating other machine learning models.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.4
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• pp.1246-1262
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• 2021

Recent studies have demonstrated the strong ability of deep convolutional neural networks (CNNs) to significantly boost the performance in single image super-resolution (SISR). The key concern is how to efficiently recover and utilize diverse information frequencies across multiple network layers, which is crucial to satisfying super-resolution image reconstructions. Hence, previous work made great efforts to potently incorporate hierarchical frequencies through various sophisticated architectures. Nevertheless, economical SISR also requires a capable structure design to balance between restoration accuracy and computational complexity, which is still a challenge for existing techniques. In this paper, we tackle this problem by proposing a competent architecture called Enhanced U-Net Network (EUN), which can yield ready-to-use features in miscellaneous frequencies and combine them comprehensively. In particular, the proposed building block for EUN is enhanced from U-Net, which can extract abundant information via multiple skip concatenations. The network configuration allows the pipeline to propagate information from lower layers to higher ones. Meanwhile, the block itself is committed to growing quite deep in layers, which empowers different types of information to spring from a single block. Furthermore, due to its strong advantage in distilling effective information, promising results are guaranteed with comparatively fewer filters. Comprehensive experiments manifest our model can achieve favorable performance over that of state-of-the-art methods, especially in terms of computational efficiency.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.5 s.311
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• pp.44-59
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• 2006

This paper describes the efficient implementation of DNA sequence generate system with genetic algorithm for reducing computation time of NACST. The proposed processor is based on genetic algerian with fitness functions which would suit the point of reference for generated sequences. In order to implement efficient hardware structure, we used the pipelined structure. In addition our design was applied the parallelism to achieve even better simulation time than the sequence generator system which is designed on software. In this paper, our hardware is implemented on the FPGA board with xc2v6000 devices. Through experiment, the proposed hardware achieves 467 times speed-up over software on a PC and sequence generate performance of hardware is same with software.

• Transactions of the Korean Society of Pressure Vessels and Piping
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• v.12 no.2
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• pp.58-65
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• 2016

Since, in case of high energy piping, steam jets ejected from the rupture zone may cause damage to nearby structure, it is necessary to design it into consideration of nuclear power plant design. For the existing nuclear power plants, the ANSI / ANS 58.2 technical standard for high-energy pipe rupture was used. However, the US Nuclear Regulatory Commission (USNRC) and academia recently have pointed out the non-conservativeness of existing high energy pipe fracture evaluation methods. Therefore, it is necessary to develop a highly reliable evaluation methodology to evaluate the behavior of steam jet ejected during high energy pipe rupture and the effect of steam jet on peripheral devices and structures. In this study, we develop a method for analyzing the impact load of a jet by high energy pipe rupture, and plan to carry out an experiment to verify the evaluation methodology. In this paper, the basic data required for the design of the jet impact load experiment equipment under construction, 1) the load change according to the jet distance, 2) the load change according to the jet collision angle, 3) the load variation according to structure diameter, and 4) the load variation depending on the jet impact position, are numerically obtained using the developed steam jet analysis technique.

• Journal of KIISE
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• v.44 no.6
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• pp.573-580
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• 2017

Despite the recent remarkable advances in the computing power of mobile devices, the heat and battery problems still restrict their performances, particularly compared to PCs. Therefore, in the application of the ray-tracing technique for high-quality rendering, the consideration of a method that traces only the secondary rays while the effects of the primary rays are generated through rasterization-based OpenGL ES rendering is worthwhile. Given that most of the rendering time is for the secondary-ray processing in such a method, a new volume-grid technique for dynamic scenes that enhances the tracing performance of the secondary rays with a low coherence is proposed here. The proposed method attempts to model all of the possible spatial secondary rays in a fixed number of sampling rays, thereby alleviating the visitation problem regarding all of the cells along the ray in a uniform grid. Also, a hybrid rendering pipeline that speeds up the overall rendering performance by exploiting the mobile-device CPU and GPU is presented.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.585-593
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• 2017

In this paper, we propose a deblocking filter hardware architecture for low-power HEVC (High-Efficiency Video Coding) in-loop for mobile systems. HEVC performs image compression on a block-by-block basis, resulting in blockage of the image due to quantization error. The deblocking filter is used to remove the blocking phenomenon in the image. Currently, UHD video service is supported in various mobile systems, but power consumption is high. The proposed low-power deblocking filter hardware structure minimizes the power consumption by blocking the clock to the internal module when the filter is not applied. It also has four parallel filter structures for high throughput at low operating frequencies and each filter is implemented in a four-stage pipeline. The proposed deblocking filter hardware structure is designed with Verilog HDL and synthesized using TSMC 65nm CMOS standard cell library, resulting in about 52.13K gates. In addition, real-time processing of 8K@84fps video is possible at 110MHz operating frequency, and operation power is 6.7mW.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.774-780
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• 2017

This paper proposes an efficient binary arithmetic encoder hardware architecture for CABAC encoding, which is an entropy coding method of HEVC. CABAC is an entropy coding method that is used in HEVC standard. Entropy coding removes statistical redundancy and supports a high compression ratio of images. However, the binary arithmetic encoder causes a delay in real time processing and parallel processing is difficult because of the high dependency between data. The operation of the proposed CABAC BAE hardware structure is to separate the renormalization and process the conventional iterative algorithm in parallel. The new scheme was designed as a four-stage pipeline structure that can reduce critical path optimally. The proposed CABAC BAE hardware architecture was designed with Verilog HDL and implemented in 65nm technology. Its gate count is 8.07K and maximum operating speed of 769MHz. It processes the four bin per clock cycle. Maximum processing speed increased by 26% from existing hardware architectures.

• Journal of the Korean Institute of Gas
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• v.12 no.3
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• pp.56-63
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• 2008

We have garnered 3,593 data of gas [Natural Gas (NG) and Liquefied Petroleum Gas (LPG)] accidents reported for 16 years from 1991, and then analyzed the accidents according to their types and causes based on the classified database. According to the results the gas leak has been the most common accident followed by the explosion and then fire accidents. The most frequent accident-occurring locations for fire, explosion and leak are recognized around the valve, hose and pipeline, respectively. In addition, we have applied the Poisson analysis to predict the most-likely probabilities of fire, explosion and release in the upcoming 5 years. From this research we have assured the successive database updating will highly improve the anticipating-probability accuracy and thus it will play a key role as a significant safety-securing guideline against the gas disasters.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.233-239
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• 2001

Among the operations in frequency domain for ADSL G.LITE Modem to perform, FFT and FEQ are most computation-intensive part, of which many researches have been focused on the efficient implementation. Previous papers suggested hardwares suitable for ADSL G.DMT system, which is not feasible for simple G.LITE system. The analysis of frequency domain operations and computational efficiency according to the allocation of hardware resources is performed in this paper. The suggested processor has the structure of one real multiplier and two real adders connected in parallel, which can perform the operations efficiently through the pipeline- and/or parallel-type job scheduling. The suggested processor uses less hardware resources than Kiss\`s ALU structure or FFT/IFFT processor suggested by Wang, so the suggested one is more suitable for G.LITE system than previous works.