• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.5
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• pp.1-9
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• 2012

In this paper, we presents the modeling and implementation of the DDS(Direct Digital synthesizer) driven offset PLL(Pghase Locked Loop) with DAC(Digital Analog Converter) for coarse tune. The PLL synthesizer was designed for minimizing the size and offset frequency and DDS technique was used for ultra low noise and fast lock up time, also DAC was used for coarse tune. The output phase noise was analyzed by superposition theory with the phase noise transfer function and noise source modeling. the phase noise prediction was evaluated by comparing with the measured data. The designed synthesizer has ultra fast lock time within 6 usec and ultra low phase noise performance of -120 dBc/Hz at 10KHz offset frequency.

• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.43-46
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• 2004

In this paper, we present a carrier phase estimation algorithm for LDPC coded systems. LDPC coded system can not achieve the ideal performance if phase offset is introduced by channel. However, the estimation of phase offset is very hard since the operating point of LDPC is very low SNR. To solve this problem, the algorithm using the tentative soft decision value and based on Maximum Likelihood (ML), was proposed in [2]. But this algorithm has problem which works only under constant phase offset. If phase offset is time variant, it has a severe degradation in performance. To solve this problem. we propose two types of estimators. symbol by symbol estimator: Unidirectional estimator (UDE) and hi-directional estimator (BDE), and sub-block estimator (SBE).

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.1 s.104
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• pp.17-23
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• 2006

This paper has presented a low phase noise oscillator using a square open loop with microstrip structure. A square open loop resonator has a large coupling coefficient value, which makes a high Q value, and has reduced phase noise. This oscillator has presented the oscillation frequency of 5.84 GHz, harmonics of -15.83 dBc and the phase noise of -111.17 dBc/Hz at the offset frequency of 100 kHz. In conclusion, the proposal structure has improved phase noise of 15 dB at the offset frequency of 100 kHz compared with the conventional structure of oscillator.

• Proceedings of the KSME Conference
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• 2001.06e
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• pp.229-234
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• 2001

An adiabatic counter-current vertical two-phase flow of air and water in narrow rectangular channels with offset strip fm was investigated experimentally. Tests were systematically performed with downward liquid superficial velocities and upward gas velocities covering 0 to 0.06 m/s and 0 to 2.5 m/s ranges, respectively. Two-phase flow regimes were classified by examining the video images of flow patterns in transparent test sections of 760 mm long and 100 mm wide channel with gaps of 3.0 and 5.0 mm. The channel average void fraction was measured by the quick-closing valve method. Unlike the flow regimes in the channels without fin, where bubbly, slug, chum, and annular flow were identified, only bubbly and chum flow regimes were found for the channels with offset strip fin. However the existence of fin in the channels showed negligible effects on the void fraction. Instead counter-current flow limitations were found to happen at lower air superficial velocity once offset strip fin was introduced in narrow rectangular channels.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.4
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• pp.653-660
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• 2001

In this paper, we designed 2303.15MHz frequency synthesizer for the purpose of the phase noise prediction. For the modeling of phase noise generated in the designed system through introducing the noise-modeling method suggested by Lascari we analyzed a variation of phase noise as according as that of offset frequency. Especially, for the third-order system of the PLL among some kinds of phase noise generated from VCO we analyzed the aspect of 1/f-noise appearing troubles in the low frequency band. Since it is difficult to analyze mathematically 1/f-noise in the third-order system of the PLL, introducing the concept of pseudo-damping factor has made an ease of the access of the 1/f-noise variance. we showed a numerical formula of 1/f-noise variance in the third-order system of the PLL which is compared with that of 1/f-noise variance in the second-order system of the PLL. As a result, In case of txco we found the reduce rapidly along the offset frequency after passed through that phase-noise was -160dBc/Hz before passed through a loop at 10kHz offset frequency and -162.6705dBc/kHz after passed through the loop, -180dBc/Hz at 100kHz offset frequency and -560dBc/kHz after passed through the loop. We can notice that the variance of third-order system more occurs (or the variance of second-order system in connection with noise bandwidth and variance factor of second-order and third-order system.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.2
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• pp.111-116
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• 2009

In this paper, we propose a phase offset estimation algorithm which is based on turbo coded digital broadcasting system. The phase estimator is an estimator outside turbo code decoder using LMS (Least Mean Square) algorithm to estimate the phase of next state. While the conventional LMS algorithm with a fixed step size is easy implemented, it has weak points that are difficult the channel estimation and tracking in the multipath environment. To resolve this problem, we propose new phase offset estimation method with a variable step size LMS (VS-LMS). Additionally, we propose a scheme which consists of a conventional LMS. The performance is verified by computer simulation according to a fixed phase offset and a increased phase offset, the proposed algorithm improve the bit error rate performance than the conventional algorithm.

• Journal of Power Electronics
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• v.15 no.6
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• pp.1593-1600
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• 2015

This paper proposes a novel compensation algorithm of current offset error for single-phase linear compressor in home appliances. In a half-bridge inverter, current offset error may cause unbalanced DC-link voltage when the DC-link is comprised of two serially connected capacitors. To compensate the current measurement error, the synchronous reference frame transformation is used for detecting the measurement error. When an offset error occurs in the output current of the half-bridge inverter, the d-axis current has a ripple with frequency equal to the fundamental frequency. With the use of a proportional-resonant controller, the ripple component can be removed, and offset error can be compensated. The proposed compensation method can easily be implemented without much computation and additional hardware circuit. The validity of the proposed algorithm is verified through experimental results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.268-272
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• 2001

In this thesis, PLVCO(Phase Locked Voltage Controlled Oscillator) using 24.42 GHz voltage controlled hair-pin resonator oscillator, Sequency divider, buffer amplifier, -10 dB directional coupler and phase detector is designed and fabricated for B-WLL. The PLVCO shows the oscillator output power of 16.5 dBm at 24.42 GHz, and phase noise of -76.3 dBc/Hz at 1001:Hz offset, -72.8dBc/Hz at 10 kHz offset from fundamental frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.11
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• pp.1074-1080
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• 2013

The low phase noise and wideband frequency synthesizer has been designed by using YTO. Offset PLL structure is used for reducing a division ratio of feedback loop. The phase noise modeling is applied to optimize loop filter of PLL and YTO module. And DDS is used as reference signal of frequency synthesizer for fine resolution. The fabricated wideband frequency synthesizer has the output frequency of 3.2 GHz to 6.8 GHz, phase noise of -107 dBc/Hz at 10 kHz offset from the carrier and frequency resolution of 1 Hz. The measured phase noise is well agreed with the simulated one.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.4
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• pp.499-506
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• 2012

In this paper, we analyze the effects of phase noise and frequency offset that cause performance degradation. Basically, we like to propose reduced PNFS(Phase Noise and Frequency offset Suppression) algorithm. The OFDM system is seriously affected by ICI component such as phase noise, frequency offset and Doppler effects. Especially, complicated processing algorithm with high complexity was required it in order to compensate those ICI components. So, we propose PNFS algorithm that can decrease complexity and compensate ICI components. We propose a method decreased complexity by approximation of parameters that affect slightly performance change and compare the quantity of conventional and revised PNFS algorithm. Also, simulation shows that BER performance of revised PNFS algorithm can be improved slightly.