• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.950-953
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• 1987

A wave difference method(WDH) phase detector for timing recovery is designed in the digital subscriber loop receiver. This paper describes the architecture and experimental results of the WDM, tankless timing extraction PLL. The results show that the designed WDM timing extraction circuit have stable jitter performance without the use of high precision LC tank circuit.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.3
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• pp.8-14
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• 1992

In this paper, the differential detection technique of multi-h CPM is introduced and described. We derived the sets of modulation index of multi-h phase codes adequate to the differential detection. The power spectra of multi-h signals with various sets of modulation index are presented and compared to those of MSK and QPSK. Error rate performances of the conventional detector and Viterbi algorithm detector of 2-h and 3-h CPM are evaluated and compared.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.3
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• pp.34-40
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• 2002

In this paper, a new encryption method for a binary image using Phase modulation and Fourier transform is proposed. For decryption we use the characteristics of square law detector. In encryption process, a key image is obtained by phase modulation of 256 level random pattern and its Fourier transformation, and input image is encrypted by Fourier transforming the multiplication of the phase modulated random pattern and phase modulated input image. The encrypted image and key image have only phase information, so they can not be copied or counterfeited and the original image can not be decrypted without the key image. To reconstruct the original image, each phase mask of the key image and the encrypted image must be placed on each path of the Mach-Zehnder interferometry with Fourier transform lens and the output image is obtained in the form of intensity in the CCD(Charge Coupled Device) camera. The real-time decryption is possible in the proposed system by use of a LCD as a phase modulator and a CCD camera as an intensity detector. The proposed method shows a good performance in the computer simulation and optical experiment as an encryption scheme.

• Journal of Electrical Engineering and Technology
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• v.11 no.1
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• pp.157-166
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• 2016

In this paper, a new sag and peak voltage detector is proposed for a single-phase inverter using delta square operation. The conventional sag detector is from a single-phase digital phase-locked loop (DPLL) that is based on d-q transformations using an all-pass filter (APF). The d-q transformation is typically used in the three-phase coordinate system. The APF generates a virtual q-axis voltage component with a 90° phase delay, but this virtual phase cannot reflect a sudden change in the grid voltage at the instant the voltage sag occurs. As a result, the peak value is drastically distorted, and it settles down slowly. A modified APF generates the virtual q-axis voltage component from the difference between the current and the previous values of the d-axis voltage component in the stationary reference frame. However, the modified APF cannot detect the voltage sag and peak value when the sag occurs around the zero crossing points such as 0° and 180°, because the difference voltage is not sufficient to detect the voltage sag. The proposed algorithm detects the sag voltage through all regions including the zero crossing voltage. Moreover, the exact voltage drop can be acquired by calculating the q-axis component that is proportional to the d-axis component. To verify the feasibility of the proposed system, the conventional and proposed methods are compared using simulations and experimental results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.12
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• pp.2716-2724
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• 2012

In this paper, a Phase Difference-to-Voltage Converter (PDVC) has been introduced into a conventional fractional-N PLL to suppress fractional spurs. The PDVC controls charge pump current depending on the phase difference of two input signals to phase frequency detector. The charge pump current decreases as the phase difference of two input signals increase. It results in the reduction of fractional spurs in the proposed fractional-N PLL. The proposed fractional-N PLL with PDVC has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.106-109
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• 1998

Wireless communication systems, in particular, must operate in a crowded electro-magnetic environmnet where in-band undesired signals are treated as noise by the receiver. These interfering signals are often random but not Gaussian Due to nongaussian noise, the distribution of the observables cannot be specified by a finite set of parameters; instead r-dimensioal sample space (pure noise samples) is equiprobably partitioned into a finite number of disjointed regions using quantiles and a vector quantizer based on training samples. If we assume that the detected symbols are correct, then we can observe the pure noise samples during the training and transmitting mode. The algorithm proposed is based on a piecewise approximation to a regression function based on quantities and conditional partition moments which are estimated by a RMSA (Robbins-Monro Stochastic Approximation) algorithm. In this paper, we develop a diversity combiner with modified detector, called Non-Linear Detector, and the receiver has a differential phase detector in each diversity branch and at the combiner each detector output is proportional to the second power of the envelope of branches. Monte-Carlo simulations were used as means of generating the system performance.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1643-1647
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• 2003

This paper, we propose a new high noise immunity phase-locked loop(PLL) which can suppress the high incident noise coupling with large amplitude and long period to the input frequency of PLL and keeps constant frequency and phase of the VCO output for providing the high stability distribution clock pulse.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1129-1132
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• 2003

본 논문에서는 위상/주파수 검출기을 설계시 문제가 되는 Reference Spur을 없게 하여 Low Noise를 구현할 수 있는 No Spike PFD(Phase Frequency Detector)를 제안한다. 위상동기루프의 특별한 형태로 차지 펌프 위상동기루프가 있다. 차지 펌프위상동기 루프는 일반적으로 3-state 위상/주파수 검출기를 이용한다. 이 3-state 위상/주파수 검출기는 기준 신호와 VCO 출력 신호의 위상차에 비례하는 디지털 파형으로 출력을 내보낸다. 차지 펌프 위상동기루프 그림 1 처럼 디지털 위상/주파수 검출기(PFD), 차지 펌프(CP), 루프 필터(LF), VCO로 구성된다. PFD 는 기준 신호와 VCO 에 의해 만들어진 출력 신호를 입력받아 각각의 위상과 주파수를 비교한다. 즉, 출력 신호가 기준 신호보다 느릴 때에는 출력 신호를 앞으로 당기기 위해서 up 신호를 넘겨주고, 출력 신호가 기준 신호보다 빠를 때에는 출력 신호를 뒤로 밀기 위해 down 신호를 넘겨준다. 차지 펌프(CP)의 전류를 Ip 라고 한다면, CP 에서 LF 로 흐르거나, LF에서 CP로 흐르는 전류 Ip의 평균량이 기준 신호와 VCO 출력 신호의 위상차에 비례하는 것이다.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3088-3090
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• 2000

In this paper, we introduce a charge pump PLL architecture which employs precharge phase frequency detector(PFD) and sequential PFD to achieve high frequency operation and fast acquisition. Operation frequency is increased by using precharge PFD when the phase difference is within -${\pi}\;{\sim}\;{\pi}$ and acquisition time is shortened by using sequential PFD and increased charge pump current when the phase difference is larger than |${\pi}$|. SO error detection range of proposed PLL structure is not limited to -${\pi}\;{\sim}\;{\pi}$. By virtue of this multi-phase frequency detector structure, the maximum operating frequency of 423MHz at 2.5V and faster acquisition were achieved by simulation.

• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.441-446
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• 2008

In this papers, a PLDRO(Phase Locked Dielectric Resonator Oscillator) is designed and implemented at the oscillator in which fundamental frequency is 18.3 GHz. The proposed PLDRO so as to improve the PLDRO of the general structure is designed to the goal of the minimize of the size and the performance improvement. Three VCO(Voltage controlled Oscillator) and the power combiner improved the output power. A VCDRO(Voltage Controlled Dielectric Resonator Oscillator) is manufactured using a varactor diode to tune oscillating frequency electrically, and its phase is locked to reference frequency by SPD(Sampling Phase Detector). This product is fabricated on Teflon substrate with dielectric constant 2.2 and device is ATF -13786 of Ka-band using. This PLDRO generates an output power of 5.67 dBm at 18.3 GHz and has the characteristics of a phase noise of -80.10 dBc/Hz at 1 kHz offset frequency from carrier, the second harmonic suppression of -33 dBc. The proposed PLDRO can be used in Ka-band satellite applications