• Journal of Communications and Networks
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• v.8 no.2
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• pp.205-211
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• 2006

This paper considers the maximum likelihood (ML) detection of 16-ary differential amplitude and phase shift keying (DAPSK) in Rayleigh fading channels. Based on the conditional likelihood function, two new receiver structures, namely ML symbol-by-symbol receiver and ML sequence receiver, are proposed. For the symbol-by-symbol detection, the conventional DAPSK detector is shown to be sub-optimum due to the complete separation in the phase and amplitude detection, but it results in very close performance to the ML detector provided that its circular amplitude decision thresholds are optimized. For the sequence detection, a simple Viterbi algorithm with only two states are adopted to provide an SNR gain around 1 dB on the amplitude bit detection compared with the conventional detector.

• Proceedings of the KIEE Conference
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• 2000.07a
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• pp.547-549
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• 2000

This paper develops phase sensitive detector for diagnosis of distribution transformers. And to detect the $tan{\delta}$ more effectively, this paper used phase sensitive detector. The sensor in oil which could be placed inside of the distribution transformer can measures the $tan{\delta}$ in oil. This could be the important factor and information, and it could be used for the basic information for a precise diagnosis. Establishment of the proposed system helps to build the confidence in monitoring of the oil-filled transformers.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.11
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• pp.60-69
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• 1996

In this study, when the coherent detector has been developed and manufactured in the receiver of radar system, we have suggested and realized the 'Frequecny-Feedback correction (FFC)' that extracts its errors affecting the performance of radar, such as amplitude imbalances (k), phase imbalance ($\varphi$) between channels and offset votlages and corrects them to improve radar performances. Applying the FFC proposed, we analyzed sthe properties of the coherent detector and compared its perfomances after and before correction procdure. After the correction sequence, the amplitude imbalance was improved upt o 2dB and the phase imbalance over 9$^{\circ}$. The image rejection ratio (IRR), one of the figures of merit of radar system, was made better above 9 dB after correcting the coherent detector which possessed 23 dB before.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.593-596
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• 2002

A design of clock and data recovery (CDR) circuit for the SONET OC-48 using a standard 0.18 ${\mu}m$ CMOS process has been performed. The phase detector and the charge pump must be able to operate at the 2.5 Gb/s input data speed and also accurately compare phase errors to reduce clock jitter. As a phase detector, the Hogge phase detector is selected but two transistors are added to improve the performance of the D-F/F. The charge pump was also designed to be placed indirectly input and output. A general ring oscillator topology is presented and simulated. It provides five-phase outputs and 220 MHz to 3.12 GHz tuning range.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.387-394
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• 2016

This paper presents a fully digital delay locked loop (DLL) that can acquire lock in four clock cycles with a resolution of a 1/4 NAND-delay. The proposed DLL with a multi-dither-free phase detector acquires the initial lock in four clock cycles with 1/2 NAND-delay. Then, it utilizes a multi-dither-free phase detector, a region accumulator, and phase blenders, to improve the resolution to a 1/4 NAND-delay. The region accumulator which continuously steers the control registers and the phase blender, adaptively controls the tracking bandwidth depending on the amount of jitter, and effectively suppresses the dithering jitter. Fabricated in a 65 nm CMOS process, the proposed DLL occupies $0.0432mm^2$, and consumes 3.7 mW from a 1.2-V supply at 2 GHz.

• Journal of IKEEE
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• v.10 no.1 s.18
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• pp.10-15
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• 2006

In this paper, a clock and data recovery (CDR) circuit for a serial link with a half rate 4x oversampling phase and frequency detector structure without a reference clock is described. The phase detector (PD) and frequency detector (FD)are designed by 4X oversampling method. The PD, which uses bang-bang method, finds the phase error by generating four up/down signal and the FD, which uses the rotational method, finds the frequency error by generating up/down signal made by the PD output. And the six signals of the PD and the FD control an amount of current that flows through the charge pump. The VCO composed of four differential buffer stages generates eight differential clocks. Proposed circuit is designed using the 0.18um CMOS technology and operating voltage is 1.8V. With a 4X oversampling PD and FD technique, tracking range of 24% at 3.125Gbps is achieved.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.8
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• pp.24-33
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• 2002

For mixed signal circuits that integrate both analog and digital blocks onto the same chip, testing the mixed circuits has become the bottleneck. Since most of mixed signal circuits are functionally tested, mixed signal testing needs expensive automatic test equipments for test input generation and response acquisition. In this paper, a new efficient BIST is developed which can be used for mixed signal circuits. In the new BIST, only faults on embedded resistances, capacitances and its combinations are considered. To guarantee the quality of chips, the new BIST performs both voltage testing and phase testing. Using these two testing modes, all the faults are detected. In order to support this technique, the voltage detector and the phase detector are developed. Experimental results prove the efficiency of the new BIST.

• Publications of The Korean Astronomical Society
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• v.21 no.2
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• pp.87-94
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• 2006

The COREA (COsmic ray Research and Education Array in Korea) project aims to build a ground array of particle detectors distributed over Korean Peninsular, through collaborations of high school students, educators, and university researchers, in order to study the origin of ultra high energy cosmic rays. COREA array will consist of about 2000 detector stations covering several hundreds of $km^2$ area at its final configuration and detect electrons and muons in extensive air-showers triggered by high energy particles. During the intial phase COREA array will start with a small number of detector stations in Seoul area schools. In this paper, we have studied by Monte Carlo simulations how to select detector sites for optimal detection efficiency for proton triggered air-showers. We considered several model clusters with up to 30 detector stations and calculated the effective number of air-shower events that can be detected per year for each cluster. The greatest detection efficiency is achieved when the mean distance between detector stations of a cluster is comparable to the effective radius of the air-shower of a given proton energy. We find the detection efficiency of a cluster with randomly selected detector sites is comparable to that of clusters with uniform detector spacing. We also considered a hybrid cluster with 60 detector stations that combines a small cluster with ${\Delta}{\iota}{\approx}100m$ and a large cluster with ${Delta}{\iota}{\approx}1km$. We suggest that it can be an ideal configuration for the initial phase study of the COREA project, since it can measure the cosmic rays with a wide range energy, i.e., $10^{16}eV{\leq}E{\leq}10^{19}eV$, with a reasonable detection rate.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.6
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• pp.865-870
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• 2001

In this paper, we analyse the effect of phase noise from PLL frequency synthesizer on 64 QAM when detecting corrupted signals. To predict the phase noise of an oscillator very accurately, we assume that the oscillator is linearly time-varying when the input impulsive current to the oscillator is small. The performance of the detector which detects the corrupted signal by oscillator phase noise is compared with that when the detector is only affected by AWGN and then analyse how much the phase noise degrades the system performance for 64 QAM.

• Proceedings of the KIEE Conference
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• 2002.04a
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• pp.183-185
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• 2002

This paper proposes the test method for the testing of a RLC parallel circuit on the electronic circuit board. This method utilizes a guarding circuit and a phase detection circuit. The guarding circuit separates electrically the tested device or circuit from printed circuit board. Phase detector estimates the phase difference from two signals, voltage and current. This method computes R. L and C value from phase difference($\theta$) and impedance value(Z) obtained by enforcing two other frequence stimulus under the guarding state.