• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.802-809
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• 2014

This paper presents a dual-mode bias modulator (BM) for complementary metal oxide semiconductor (CMOS) power amplifiers (PAs). The BM includes a hybrid buck converter and a normal buck converter for an envelope tracking (ET) mode for high output power and for an average power tracking (APT) mode for low output power, respectively. The dual-mode BM and CMOS PA are designed using a $0.18-{\mu}m$ CMOS process for the 1.75 GHz band. For the 16-QAM LTE signal with a peak-to-average power ratio of 7.3 dB and a bandwidth of 5 MHz, the PA with the ET mode exhibited a poweradded efficiency (PAE) of 39.2%, an EVM of 4.8%, a gain of 19.0 dB, and an adjacent channel leakage power ratio of -30 dBc at an average output power of 22 dBm, while the stand-alone PA has a PAE of 8% lower at the same condition. The PA with APT mode has a PAE of 21.3%, which is an improvement of 13.4% from that of the stand-alone PA at an output power of 13 dBm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.9A
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• pp.795-802
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• 2005

Binary CDMA(B-CDMA) is a new modulation scheme that employs a constant envelope modulation scheme By quantizing the envelope of multi-codes CDMA signal into a small number of levels, the B-CDMA can reduce the peak-to-average power ratio, while preserving the advantages of CDMA signaling such as the soft capacity and robustness to interference. In this paper, we analyze the performance of B-CDMA systems in multi-path channel assuming that the spreading factor is not too small. Finally, the analytic results are verified by computer simulation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.3
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• pp.292-299
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• 2015

An envelope elimination and restoration transmitter that uses a tri-level envelope encoding scheme is presented for improving the efficiency and linearity of the system. The proposed structure amplifies the same magnitude signal regardless of the input peak-to-average power ratio and reduces the quantization noise by spreading out the noise to the out-of-band frequency, resulting in the enhancement of power efficiency. An improved linearity is also obtained by providing a new timing mismatch calibration technique between the envelope and phase signal. Implementation in a 130 nm CMOS process, transmitter measurements on a 20-MHz long-term evolution input signal show an error vector magnitude of 3.7 % and an adjacent channel leakage ratio of 37.5 dBc at 2.13 GHz carrier frequency.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.951-954
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• 2000

In this paper, we present a multi-code parallel combinatory CDMA system using bi-orthogonal modulation to reduce envelope variation and improve bit error. .rate (BER) performance. In general, the dynamic range of the amplitude of the transmit signal is very large in the case of conventional multi-code CDMA systems, resulting in severe nonlinear distortion due to high power amplifier and thus significant BER performance degradation. The proposed system exhibits reduction of peak-to-average power ratio (PAPR) of the transmit signal amplitudes and significant performance improvement. We verify the performance of the proposed system by computer simulations under AWGN channel and flat fading channel.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.8
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• pp.851-856
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• 2010

This paper presents an efficiency enhancement for the balanced power amplifier using DBS(Dynamic Bias Switching) method which dynamically provides the power amplifier with two bias voltage levels according to the input envelope signal. In order to apply the dynamic biases to each side of the balanced power amplifier, two switching stages are adopted. Using an OFDM signal with a bandwidth of 20 MHz and a PAR(Peak to Average Ratio) of 8.5 dB, 6 % of PAE(Power-Added Efficiency) is improved at an output power of 42.5 dBm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.8
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• pp.813-822
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• 2009

We have investigated operation of a 1:2:2 asymmetric 3-stage Doherty PA(Power Amplifier) and implemented using the Freescale's 4 W, 10 W PEP LDMOSFETS at 1 GHz. By employing the three peak efficiency characteristics, compared to the two peak N-way Doherty PA, the asymmetric 3-stage Doherty can overcome the serious efficiency degradation along the backed-off output power region and maximize the average efficiency for the modulation signal. To maximize the efficiency characteristic, the inverse class F PA has been designed as carrier and peaking amplifiers. Furthermore, to extract the proper load modulation operation, the adaptive gate bias control signal has been applied to the two peaking PAs based on the envelope tracking technique. For the 802.16e Mobile WiMAX(World Interoperability for Microwave Access) signal with 8.5 dB PAPR(Peak to Average Power Ratio), the proposed Doherty PA has shown 55.46 % of high efficiency at an average output power of 36.85 dBm while maintaining the -37.23 dB of excellent RCE(Relative Constellation Error) characteristic. This is the first time demonstration of applying the saturated PA and adaptive gate bias control technique to the asymmetric 3-stage Doherty PA for the highly efficient transmitter of the base-station application.

• Journal of Communications and Networks
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• v.12 no.6
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• pp.544-557
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• 2010

This paper addresses the problem of controlling the envelope's power peak of single carrier modulated signals, band limited by root-raised cosine (RRC) pulse shaping filters, in order to reduce power amplifier back-off for very small aperture terminals ground stations. Magnitude modulation (MM) is presented as a very efficient solution to the peak-to-average power ratio problem. This paper gives a detailed description of the MM concept and its recent evolutions. It starts by extending the look-up-table (LUT) based approach of the MM concept to M-ary constellations with M ${\leq}$ 16. The constellation and RRC symmetries are explored, allowing considerable reduction on LUT computation complexity and storage requirements. An effective multistage polyphase (MPMM) approach for the MM concept is then proposed. As opposed to traditional LUT-MM solutions, MM coefficients are computed in real-time by a low complexity multirate filter system. The back-off from high-power amplifier saturation is almost eliminated (reduction is greater than 95%) with just a 2-stage MPMM system even for very demanding roll-off cases (e.g., ${\alpha}$ = 0,1). Also, the MPMM is independent of modulation in use, allowing its easy application to constellations with M > 16.

• Journal of electromagnetic engineering and science
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• v.7 no.4
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• pp.147-153
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• 2007

This paper represents an analog predistortion linearizer for the high power amplifier with low memory effect. The high power amplifier is implemented using a 90-W peak envelope power(PEP) LDMOSFET at 2.14-GHz and an envelope short matching topology is applied at the active ports to minimize the memory effect. The analog predistortion circuit comprises the fundamental path and the cuber and quintic generating circuits, whose amplitudes and phases can be controlled independently. The predistortion circuit is tested for two-tone and wide-band code division multiple access(WCDMA) 4FA signals. For the WCDMA signal, the adjacent channel leakage ratios(ACLRs) at 5 MHz offset are improved by 12.4 dB at average output powers of 36 dBm and 42 dBm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.8
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• pp.795-801
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• 2014

This paper presents an efficiency enhancement for the high power amplifier using DDBS(Digitally-controlled Dynamic Bias Switching) method which dynamically provides the power amplifier with two bias voltage levels according to the input envelope signal. It is quite easy to adjust the control signal by using a digital processing. The fabricated DDBS PA was evaluated using an 64 QAM FDD LTE signal, which has a center frequency of 2.6 GHz, a bandwidth of 10 MHz and a PAPR of 9.5 dB. The DDBS increases the power amplifier's PAE(Power-Added Efficiency) from 40.9 % to 48 %, at an average output power level of 43 dBm.

• Wind and Structures
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• v.29 no.5
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• pp.323-337
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• 2019

Wind tunnel testing technique has been established as a powerful experimental method for predicting wind-induced loads on high-rise buildings. Accurate assessment of the design wind load combinations for tall buildings on the basis of wind tunnel tests is an extremely important and complicated issue. The traditional design practice for determining wind load combinations relies partly on subjective judgments and lacks a systematic and reliable method of evaluating critical load cases. This paper presents a novel optimization-based framework for determining wind tunnel derived load cases for the structural design of wind sensitive tall buildings. The peak factor is used to predict the expected maximum resultant responses from the correlated three-dimensional wind loads measured at each wind angle. An optimized convex hull is further developed to serve as the design envelope in which the peak values of the resultant responses at any azimuth angle are enclosed to represent the critical wind load cases. Furthermore, the appropriate number of load cases used for design purposes can be predicted based on a set of Pareto solutions. One 30-story building example is used to illustrate the effectiveness and practical application of the proposed optimization-based technique for the evaluation of peak resultant wind-induced load cases.