• 제목/요약/키워드: pattern sensitive faults

검색결과 12건 처리시간 0.017초

Diagnosis of Plasma Equipment using Neural Network and Impedance Match Monitoring

  • Byungwhan Kim
    • KIEE International Transaction on Systems and Control
    • /
    • 제2D권2호
    • /
    • pp.120-124
    • /
    • 2002
  • A new methodology is presented to diagnose faults in equipment plasma. This is accomplished by using neural networks as a pattern recognizer of radio frequency (rf) impedance match data. Using a match monitor system, the match data were collected. The monitor system consisted mainly of a multifunction board and a signal flow diagram coded by Visual Designer. Plasma anomaly was effectively represented by electrical match positions. Twenty sets of fault-symptom patterns were experimentally simulated with variations in process factors, which include rf source power, pressure, Ar, and $O_$2 flow rates. As an input to neural networks, two means and standard deviations of positions were used as well as a reflected power. Diagnostic accuracy was measured as a function of training factors, which include the number of hidden neurons, the magnitude of initial weights, and two gradients of neuron activation functions. The accuracy was the most sensitive to the number of hidden neurons. Interaction effects on the accuracy were also examined by performing a 2$^$4 full factorial experiment. The experiments were performed on multipole inductively coupled plasma equipment.

  • PDF

대용량 메모리의 이웃 패턴 감응 고장의 효율적 테스팅을 위한 메모리 구조 (Parallel Accessible Design for Detection of Neighborhood Pattern Sensitive Faults in High Density DRAMs)

  • 김주엽;홍성제;김종
    • 한국정보과학회:학술대회논문집
    • /
    • 한국정보과학회 2004년도 가을 학술발표논문집 Vol.31 No.2 (1)
    • /
    • pp.649-651
    • /
    • 2004
  • 본 논문은 메모리 집적도의 증가로 인해 많이 발생하는 이웃 패턴 감응 고장에 대한 효율적인 테스팅 방법을 제안하고 있다. 기존의 테스팅 방법에서는 비트 단위의 순차적인 셀 어레이 접근으로 인해 결함 검출율과 테스팅 시간에 있어서 문제를 가지고 있다. 이러한 문제들을 본 논문에서는 이웃 패턴 감응 고장을 효율적으로 검출 할 수 있는 타일 방식으로 셀 어레이를 구분하여 이웃 셀의 영역을 제한한다 그리고 기본 셀과 이웃 셀에 필요한 패턴을 병렬로 입출력시킬 수 있는 병렬 접근 디코더와 검출기를 설계함으로써 전체 테스팅 시간을 줄이고 결함 검출율을 높일 수 있는 방법을 제안한다.

  • PDF