• The KIPS Transactions:PartC
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• v.9C no.5
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• pp.725-732
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• 2002

Presented is a Genetic Algorithm (GA) for dynamic partitioning an ATM LANE(LAN Emulation) network. LANE proves to be one of the best solutions to provide guaranteed Quality of Service (QoS) for mid-size campus or enterprise networks with minor modification of legacy LAN facilities. However, there are few researches on the efficient LANE network operations to deal with scalability issues arising from broadcast traffic delivery. To cope with this scalability issue, proposed is a decision model named LANE Partitioning Problem (LPP) which aims at partitioning the entire LANE network into multiple Emulated LANs (ELANS), each of which works as an independent virtual LAN.

• Journal of Broadcast Engineering
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• v.27 no.3
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• pp.361-368
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• 2022

Quaternary tree plus multi-type tree (QT+MTT) structure was adopted in the Versatile Video Coding (VVC) standard as a block partitioning tool. QT+MTT provides excellent coding gain; however, it has huge encoding complexity due to the flexibility of the binary tree (BT) and ternary tree (TT) splits. This paper proposes a fast inter coding unit (CU) partitioning algorithm for BT and TT split types based on prediction accuracy functions using the mean of the absolute error (MAE). The MAE-based decision model was established to achieve a consistent time-saving encoding with stable coding loss for a practical low complexity VVC encoder. Experimental results under random access test configuration showed that the proposed algorithm achieved the encoding time saving from 24.0% to 31.7% with increasing luminance Bjontegaard delta (BD) rate from 1.0% to 2.1%.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.541-544
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• 2004

This paper presents a new circuit panitioning algorithm using wire redundancy removal. This algorithm consist of the two steps. In the first step. We propose a new IIP(Iterative Improvement Partitioning) technique that selects the method to choice cells according to improvement status using two kinds of bucket structures, the one kept by total gain, and the other by updated gain. In the second step, we select the target wire in the cut-set. We add a alternative wire in the circuit to remove the target wire. For this we use wire redundancy removal and addition method The experimental results on MCNC benchmark circuits show improvement up to $41-50\%$ in cut-size over previous algorithms

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.1011-1014
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• 1999

In this paper, a new algorithm has been presented that helps to preserve diversity as well as to enhance the convergence speed of the evolutionary programming. This algorithm is based on the cell partitioning of search region for preserving the diversity. Until now, the greater part of researches is not concerned about preserving the diversity of individuals in a population but improving convergence speed. Although these evolutions are started from multi-point search at the early phase, but at the end those search points are swarming about a one-point, the strong candidate. These evolutions vary from the original idea in some points such as multi-point search. In most case we want to find the only one point of the best solution not several points in the vicinity of that. That is why the cell partitioning of search region has been used. By restricting the search area of each individual, the diversity of individual in solution space is preserved and the convergence speed is enhanced. The efficiency of the proposed algorithm has been verified through benchmark test functions.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1025-1030
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• 2005

With the increasing use of multimedia technologies, image compression requires higher performance as well as new functionality. Specially, in the specific area of still image encoding, a new standard, JPEG2000 was developed. This paper proposed Set Partitioning Sorting Algorithm that uses a method to optimized selection of threshold from feature of wavelet transform coefficients and to removes sign bit in LL area on JPEG2000. Experimental results show the proposed algorithm achieves more improved bit rate.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2001.06a
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• pp.73-76
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• 2001

High-level synthesis generates a structural design that implements the given behavior and satisfies design constraints for area, performance, power consumption, packaging, testing and other criteria. Thus, high-level synthesis generates that register-transfer(RT) level structure from algorithm level description. High-level synthesis consist of compiling, partitioning, scheduling. In this paper, we proposed the efficient scheduling algorithm that find the number of the functional unit and scheduling into the minimum control step with silicon area resource constrained.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1724-1727
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• 2002

Asynchronous circuits have the potential to solve the problems related to parameter variations such as gate delays in deep sub-micron technologies. However, current CAD tools for large-scale asyn-chronous circuits partition specification irrelevantly, because these tools cannot control the granularity of circuit decomposition. In this paper we propose a hierarchical Control/Data Flow Graph (CDFG) containing nodes that are flexibly partitioned or merged into other nodes. We show a partitioning algorithm for such CDFGs to generate handleable Signal Transition Graphs (STGs) for asynchronous synthesis tools. The algorithm a1lows designers to assign the maximum number of signals of partitioned nodes considering of timality. From an experiment, this algorithm can flexibly partition and result in more compact asynchronous controllers.

• Proceedings of the KIEE Conference
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• 1996.11a
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• pp.291-293
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• 1996

Logic simulation is playing a very important role for design verification as circuits are larger and more complicated. However unknown values in 3 value simulators may generate the X-propagation problem which makes inaccurate output values. In this paper, a new partitioning method and a new simulation algorithm are developed to deal with the X-propagation problem efficiently. The new algorithm can optimize simulation time and accuracy by controlling partition depth. Benchmark results prove the effectiveness of the new simulation algorithm.

• The Transactions of the Korea Information Processing Society
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• v.5 no.8
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• pp.1985-1996
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• 1998

A parallelising algorithm for partitioning and mapping methods of matrix/vector multiplication into linear processor array/VLW simulator is presented in this paper. First we discuss the mapping methods for input matrix or vector into the arbitrarily size of processor arrays. Then, we show partitioning the algorithmss of the large size of computational problem into the size of the processor array. We execute the algorithm on VLIW simuhator and show to effectiviness of algorithm. The result which we achived better parallelising performance on our VLIW simulator dsign than on linear processor array.

• Journal of Computing Science and Engineering
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• v.4 no.3
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• pp.207-224
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• 2010

This paper presents a compression scheme for mesh geometry, which is suitable for mobile graphics. The main focus is to enable real-time decoding of compressed vertex positions while providing reasonable compression ratios. Our scheme is based on local quantization of vertex positions with mesh partitioning. To prevent visual seams along the partitioning boundaries, we constrain the locally quantized cells of all mesh partitions to have the same size and aligned local axes. We propose a mesh partitioning algorithm to minimize the size of locally quantized cells, which relates to the distortion of a restored mesh. Vertex coordinates are stored in main memory and transmitted to graphics hardware for rendering in the quantized form, saving memory space and system bus bandwidth. Decoding operation is combined with model geometry transformation, and the only overhead to restore vertex positions is one matrix multiplication for each mesh partition. In our experiments, a 32-bit floating point vertex coordinate is quantized into an 8-bit integer, which is the smallest data size supported in a mobile graphics library. With this setting, the distortions of the restored meshes are comparable to 11-bit global quantization of vertex coordinates. We also apply the proposed approach to compression of vertex attributes, such as vertex normals and texture coordinates, and show that gains similar to vertex geometry can be obtained through local quantization with mesh partitioning.