• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.351-354
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• 2004

This thesis presents Bipolar transistor with SAVEN(Self-Aligned VErtical Nitride) structure as a high-speed device which is essential for high-speed system such as optical storage system or mobile communication system, and proposes 0.8${\mu}m$ BiCMOS Process which integrates LDD nMOS, LDD pMOS and SAVEN bipolar transistor into one-chip. The SPICE parameters of LDD nMOS, LDD pMOS and SAVEN Bipolar transistor are extracted, and comparator operating at 500MHz sampling frequency is designed with them. The small Parasitic capacitances of SAVEN bipolar transistor have a direct effect on decreasing recovery time and regeneration time, which is helpful to improve the speed of the comparator. Therefore the SAVEN bipolar transistor with high cutoff frequency is expected to be used in high-speed system.

• 한국산업정보학회:학술대회논문집
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• 한국산업정보학회 2002년도 춘계학술대회 논문집
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• pp.195-199
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• 2002

This paper describes the effect of substrate back bias of CMOS Inverter. When the substrate back bias applied in body, the MOS transistor threshold voltage increased and drain saturation current decreased. The back gate reverse bias or substrate bias has been widely utilized and the following advantage has suppressing subthreshold leakage, lowering parasitic junction capacitance, preventing latch up or parasitic bipolar transistor, etc. When the reverse voltage applied substrate, this paper stimulated the propagation delay time CMOS inverter.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권3호
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• pp.401-410
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• 2017

In this work, we show that the excessive lattice heating problem due to parasitic pnp transistor action in the diode electrostatic discharge (ESD) protection device in the diode input protection circuit, which is favorably used in CMOS RF ICs, can be solved by adopting a symmetrical cathode structure. To explain how the recipe works, we construct an equivalent circuit for input human-body model (HBM) test environment of a CMOS chip equipped with the diode protection circuit, and execute mixed-mode transient simulations utilizing a 2-dimensional device simulator. We attempt an in-depth comparison study by varying device structures to suggest valuable design guidelines in designing the protection diodes connected to the $V_{DD}$ and $V_{SS}$ buses. Even though this work is based on mixed-mode simulations utilizing device and circuit simulators, the analysis given in this work clearly explain the mechanism involved, which cannot be done by measurements.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.274-280
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• 2007

This paper demonstrates an efficiency improvement of the class E power amplifier (PA) by tuning-out the input capacitance ($C_{IN}$) of the power HBT with a shunt inductance. In order to obtain high output power, the PA needs the large emitter size of a transistor. The larger the emitter size, the higher the parasitic capacitance. The parasitic $C_{IN}$ affects the distortion of the voltage signal at the base node and changes the duty cycle to decrease the PA's efficiency. Adopting the L-C resonance, we obtain a remarkable efficiency improvement of as much as 7%. This PA exhibits output power of 29 dBm and collector efficiency of 71% at 1.9 GHz.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1995년도 추계학술대회 논문집
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• pp.158-162
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• 1995

We report rf and power characteristics of AlGaAs/GaAs Heterojunction Bipolar Transistor (HBTs) for X-band power applications. HBTs have been fabricated with polyimide a an interlayer dielectric. By characterizing the DC and RF characteristics we obtained the maximum current gain of 45, BV$\_$CEO/ of 10 V, fT of 30 GHz and f$\_$max/ of 17 GHz for device with 6x14$\mu\textrm{m}$$^2$emitter size. To extract accurate equivalent parameters, the De-embedded method was applied for extraction of parasitic parameters and the calculation of circuit equations for intrinsic parameters. Based on the Load-pull method, power characteristics was simulated and measured to get the maximum output power of the device.

• 전자공학회논문지A
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• 제30A권10호
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• pp.41-50
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• 1993

This paper describes the fabrication process and electrical characteristics of PSA (Polysilicon Self-Align) bipolar transistors with a thin base width of 1100.angs.. To realize this shallow junction depth, one-step rapid thermal annealing(RTA) technology has been applied instead of conventional furnace annealing process. It has been shown that the series resistances and parasitic capacitances are significantly reduced in the device with emitter area of 1${\times}4{\mu}m^{2}$. The switching speed of 2.4ns/gate was obtained by measuring the minimum propagation delay time in the I$^{2}$L ring oscillator with 31 stages.

• 전자공학회논문지
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• 제49권12호
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• pp.194-200
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• 2012

본 논문에서는 SPICE 시뮬레이션을 위한 고전압 insulated gate bipolar transistor(IGBT)의 개선된 모델을 제안하였다. IGBT를 부속 소자인 MOSFET과 BJT의 조합으로 구성하고, 각 소자의 각종 파라미터 값을 조절하여 기본적인 전류-전압 특성과 온도변화에 따른 출력특성의 변화 등을 재현하였다. 그리고 비선형적인 리버스 트랜스퍼 커패시턴스 등의 기생 커패시턴스의 전압에 따른 변화를 높은 정확도로 재현하기 위해, 복수의 접합 다이오드, 이상적인 전압 및 전류 증폭기, 전압제어 저항, 저항과 커패시터 수동소자 등을 추가하였다. 본 회로모델을 1200V급의 트렌치 게이트 IGBT의 모델링에 이용하였으며, 실측자료와 비교하여 통해 모델의 정확도를 검증하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 춘계학술대회 논문집 디스플레이 광소자 분야
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• pp.187-190
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• 2000

We fabricated general photo diode, surface etched photo diode and floating gate MOSFET by CMOS process. In a design stage, we expect that surface etched photo diode will be improved as to photo sensitivity. However, because the surface of silicon was damaged in etching process, the surface etched diode had a high dark current as well as low photo current level. Finally, we examined the current-voltage properties for the floating gate MOSFET on n-well and confirmed that the device can be act as an efficient photo-sensor. The floating gate MOSFET was operated in parasitic bipolar transistor mode.

• 전자공학회논문지A
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• 제31A권12호
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• pp.64-70
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• 1994

In this paper, we inverstigated how a parricular internal inverter circuit, which is located far from the input protection in CMOS DRAM, can be easily damaged by external ESD stress, while the protection circuit remains intact. It is shown in a mega bit DRAM that the internal circuit can be safe from ESD by simply improving the input protection circuit. An inverter, which consists of a relatively small NMOSFET and a very large PMOSFET, is used to speed up DRAMs, and the small NMOSFET is vulnerable to ESD in case that the discharge current beyond the protection flows through the inverter to Vss or Vcc power lines on chip. This internal circuit damage can not be detected by only measuring input leakage currents, but by comparing the standby and on operating current before and after ESD stressing. It was esperimentally proven that the placement of parasitic bipolar transistor between input pad and power supply is very effective for ESD immunity.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 추계학술대회 논문집 학회본부 C
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• pp.971-973
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• 1999

채널길이에 따른 n-채널과 p-채널 poly-Si TFT's를 제작하고 그 전기적 특성을 분석하였다. n-채널과 p-채널소자는 공통적으로 기생바이폴라트 랜지스터현상(parasitic bipolar transistor action)에 의한 kink 효과, 전하공유(charge sharing)에 의한 문턱전압의 감소, 소오스와 드레인 근처의 결함에 의한 RSCE(reverse short channel effect) 효과, 수직전계에 의한 이동도의 감소, 그리고 avalanche 증식에 의한 S-swing의 감소가 나타났다. n-채널은 p-채널 보다 더 큰 kink, 이동도, S-swing의 변화가 나타났으며, 높은 드레인 전압에서의 문턱전압의 이동은 avalanche 증식(multiplication)에 의한 것이 더 우세한 것으로 나타났다. 누설전류의 경우, 채널 길이가 짧아짐에 따라 n-채널은 큰 증가를 나타냈으나 p-채널의 경우는 변화가 나타나지 않았다.