• 대한전자공학회논문지
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• 제21권3호
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• pp.13-18
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• 1984

Horizontal microprogram에서 MO'S(microoper&titans)의 concurrency와 resource의 할당을 고려하여 MO'S을 병렬로 수행할 수 있는 알고리즘을 제안한다. 본 알고리즘은 SLM(straight line microprogram) 상에 있는 각 MO에 weight를 부여함으로써 병렬 실행될 수 있는 MO'S을 1개의 MI(microinstruction)으로 결합하여 전체 MI수를 최소화시킴으로써 실행 시간과 microprogramed 디지탈 시스템의 제어기억장치 크기(space)를 감소시키는 결과를 얻을 수 있다.

• 전자공학회논문지A
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• 제33A권5호
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• pp.155-164
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• 1996

The architecture of a programmable video codec IC is described that employs multiple vector processors in a single chip. The vector processors operate in parallel and communicate with one another through on-chip shared memories. A single scalar control processor schedules each vector processor independently to achieve real-tiem video coding with special vector instructions. With programmable interconnection buses, the proposed architecture performs multi-processing of tasks and data in video coding. Therefore, it can provide good parallelism as well as good programmability. especially, it can operate multithread video coding, which processes several independent image sequences simultaneously. We explain its scheduling, multithred video coding, and vector processor architectures. We implemented a prototype video codec with a 0.8um CMOS cell-based technology for the multi-standard videophone. This codec can execute video encoding and decoding simultaneously for the QCIF image at a frame rate of 30Hz.

• 대한전자공학회논문지
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• 제27권6호
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• pp.963-971
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• 1990

This paper proposes a memory intensive VLSI architecture for the realization of real-time 3x3 neighborhood processor based on the distributed arithmetic. The proposed architecture is characterized by a bit serial and multi-kernel parallel processing which exploits the pixel kernel parallelism and concurrency. The chip implements 8 neighborhood processing elements in parallel with efficirnt input and output modules which operate concurrently. Besides the a4chitectural design of a neighborhood processor, the design methodology using module generator concept has been considered and MOGOT(MOdule Generator Oriented VLSI design Tool) has been constructed based on the workstation. Based on these design environments MOGOT, it has been shown that the main part of the suggested architecture can be designed efficiently using 2\ulcorner double metal CMOS technology. It includes design of input delay and data conversion module, look-up table for inner product operation, carry save accumulator, output data converter and delay module, and control module.

• Journal of Preventive Medicine and Public Health
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• 제21권2호
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• pp.245-250
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• 1988

For the evaluation of change of FVC and $FEV_1$ after discontinuance of bronchodilator in the coal workers' pneumoconiosis patients, 17 pairs of patients were selected. They were matched by the age(${\pm}5$ y.o.) and the type of ventilatory impairment. Pulmonary function was measured 2 times bimonthly before and after the drug discontinuance discontinued after measurement of PFT for 2 times. In case group the bronchodilator was discontinued after measurement of PFT for 2 times. In control group there was no interruption of medication. FVC, $FEV_1$ decreased in both group as measurement progress. Simple linear regression coefficients against the month of measurement were calculated in both group and tested for parallelism between two groups. The results of test revealed that both regression coefficients were parallel. So in conclusively, discontinuance of medication of bronchodilator for coal workers pneumoconiosis patients has no effect on the decreasing rate of FVC, $FEV_1$.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 정기총회 및 창립40주년기념 학술대회 학회본부
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• pp.90-94
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• 1987

A structured user-friendly procedures which enable users to program in GRAFCET form directly from sequence specifications have been developed. Using these procedures, we can program the programmable logic controller (PLC) in sequential control and realize programming, debugging, and real-time monitoring. GRAFCET has many advantages like parallelism expression, so we can expect higher productivity and easier maintenance than boolean language or relay-ladder diagram specification when adapts them to PLC.

• 한국언어정보학회지:언어와정보
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• 제7권2호
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• pp.117-137
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• 2003

This paper attempts to provide an alternative analysis involving categorical issues related to English gerunds. Especially, this paper rejects Maulof's approach that creates a new syntactic category gerund by mixing nominal and verbal categories. This paper identifies two syntactic structures in English gerunds: nominal gerunds and verbal gerunds. This distinction is based on syntactic and semantic characteristics of each type and is intended to account for the external distribution and endocentricity of the construction. Treating verbal gerunds syntactically as verbal categories, this paper proposes that English verbal gerunds act like other verbal categories such as infinitives whereas nominal gerunds behaves much like derived nominals. This paper proposes a few lexical rules that can take care of the two types of gerunds. The proposal can be extended to prepositional complements as well as sentential subject positions. This proposal not only resolves the issues involving distributional properties of the gerund construction but also captures syntactic parallelism observable between gerunds and other verbal constructions in English.

• 한국정보과학회논문지:시스템및이론
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• 제26권1호
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• pp.98-106
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• 1999

본 논문에서는 대용량 입출력을 수행하는 태스크의 QoS를 제어하기 위한 방법으로사용자가 시스템에 입출력 요구시 요구 대역폭을 제시하고, 파일시스템에서 디스크개소와 입출력 이벤트를 고려하여 입출력의 병렬성을 제어함으로써 QoS를 제어하는 방법을 제안하였다. 그리고, 시스템에서 각 태스크가 주어진 병렬성을 가지고 입출력을 진행하고 있을 때, 요구 대역폭을 가지고 입출력을 요구하는 태스크의 대역폭을 만족시키기 위한 병렬성을 계산하는 분석 모델을 유도하였다. 그리고, 디스크 입출력의 병렬성을 이용하여 대용량 입출력의 QoS를 효율적으로 제어할 수 있음을 분석 모델의 결과를 통해 검증하였다.

• 예술인문사회 융합 멀티미디어 논문지
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• 제4권2호
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• pp.369-378
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• 2014

The Reed-Muller code is one of the efficient algorithms for multiple bit error correction, however, its high-computation requirement inherent in the decoding process prohibits its use in practical applications. To solve this problem, this paper proposes a graphics processing unit (GPU)-based parallel error control approach using Reed-Muller R(r, m) coding for real-time wireless communication systems. GPU offers a high-throughput parallel computing platform that can achieve the desired high-performance decoding by exploiting massive parallelism inherent in the algorithm. In addition, we compare the performance of the GPU-based approach with the equivalent sequential approach that runs on the traditional CPU. The experimental results indicate that the proposed GPU-based approach exceedingly outperforms the sequential approach in terms of execution time, yielding over 70× speedup.

• 대한전기학회논문지:시스템및제어부문D
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• 제54권12호
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• pp.723-731
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• 2005

The $4{\times}4$ homogeneous transformation matrix is a compact representation of orientation and position of an object in robotics and computer graphics. A coordinate transformation is accomplished through the successive multiplications of homogeneous matrices, each of which represents the orientation and position of each corresponding link. Thus, for real time control applications in robotics or animation in computer graphics, the fast multiplication of homogeneous matrices is quite demanding. In this paper, a parallel-architecture vector processor is designed for this purpose. The processor has several key features. For the accuracy of computation for real application, the operands of the processors are floating point numbers based on the IEEE Standard 754. For the parallelism and reduction of hardware redundancy, the processor takes column vectors of homogeneous matrices as multiplication unit. To further improve the throughput, the processor structure and its control is based on a pipe-lined structure. Since the designed processor can be used as a special purpose coprocessor in robotics and computer graphics, additionally to special matrix/matrix or matrix/vector multiplication, several other useful instructions for various transformation algorithms are included for wide application of the new design. The suggested instruction set will serve as standard in future processor design for Robotics and Computer Graphics. The design is verified using FPGA implementation. Also a comparative performance improvement of the proposed design is studied compared to a uni-processor approach for possibilities of its real time application.

• 정보처리학회논문지D
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• 제15D권1호
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• pp.87-98
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• 2008

임베디드 시스템의 하드웨어 구성요소들에 대한 성능 고도화가 요구됨에 따라 이에 탑재될 소프트웨어의 개발 방법도 영향을 받고 있다. 특히 MPSoC와 같은 고가의 하드웨어 아키텍처에서는 효율적인 자원의 사용 및 성능의 향상을 위해 소프트웨어 측면에서의 고려가 필수적으로 요구된다. 따라서 본 연구에서는 임베디드 소프트웨어 개발과정에서 멀티프로세서 기반의 하드웨어 아키텍처를 고려하는 소프트웨어 태스크의 분할기법을 제시한다. 제시하는 기법은 UML 기반의 소프트웨어 모델을 CBCFG (Constraints-Based Control Flow Graph)로 변환하고, 이를 병렬성과 데이터 의존성을 고려한 소프트웨어 컴포넌트로 분할하는 기법이다. 이러한 기법은 임베디드 소프트웨어의 플랫폼 의존적인 모델 개발과 태스크 성능 예측 등을 위한 자료로 활용할 수 있다.