• Title/Summary/Keyword: parallelism control

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Dynamic Control of A Sik-link Robot Using Neural Networks (신경회로를 이용한 6축 Robot의 Dynamic Control)

  • Joe, Moon-Jeung;Oh, Se-Young
    • Proceedings of the KIEE Conference
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    • 1990.07a
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    • pp.500-503
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    • 1990
  • Neural network is a computational model of the biological nervous system developed to exploit its intelligence and parallelism. Applying neural networks to robots creates many advantages over conventional control methods such as learning, real-time control, and continuous performance improvement through training and adaptation. In this paper, dynamic control of a six-link robot will be presented using neural networks. The neural network model used in this paper is the backpropagation network. Simulated control of the PUMA 560 arm shows that it can move at high speed as well as adapt to unforseen load changes. The results are compared with the conventional PD control scheme.

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Inverse Dynamic Torque Control of a Six-Jointed Robot Arm Using Neural networks (신경회로를 이용한 6축 로보트의 역동력학적 토크제어)

  • 오세영;조문정;문영주
    • The Transactions of the Korean Institute of Electrical Engineers
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    • v.40 no.8
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    • pp.816-824
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    • 1991
  • It is well known that dynamic control is needed for fast and accurate control. Neural networks are ideal for representing the strongly nonlinear relationship in the dynamic equations including complex unmodeled effects. It thus creates many advantages over conventional methods such as simple, fast and accurate control through neural network's inherent learning and massive parallelism. In this paper, dynamic control of the full six degrees of freedom of an industrial robot arm will be presented using neural networks. Moreover, through application to a real robot the usefulness of neurocontrol is demonstrated. The back propagation and feedback-error learning is used to train the neurocontroller. Simulated control of a PUMA 560 arm demonstrates that it moves at high speed with good accuracy and generalizes over untrained trajectories as well as adapt to unforseen load changes and sensor noise.

A Study on the Neuro-Fuzzy Control for an Inverted Pendulum System (도립진자 시스템의 뉴로-퍼지 제어에 관한 연구)

  • 소명옥;류길수
    • Journal of Advanced Marine Engineering and Technology
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    • v.20 no.4
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    • pp.11-19
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    • 1996
  • Recently, fuzzy and neural network techniques have been successfully applied to control of complex and ill-defined system in a wide variety of areas, such as robot, water purification, automatic train operation system and automatic container crane operation system, etc. In this paper, we present a neuro-fuzzy controller which unifies both fuzzy logic and multi-layered feedforward neural networks. Fuzzy logic provides a means for converting linguistic control knowledge into control actions. On the other hand, feedforward neural networks provide salient features, such as learning and parallelism. In the proposed neuro-fuzzy controller, the parameters of membership functions in the antecedent part of fuzzy inference rules are identified by using the error backpropagation algorithm as a learning rule, while the coefficients of the linear combination of input variables in the consequent part are determined by using the least square estimation method. Finally, the effectiveness of the proposed controller is verified through computer simulation of an inverted pendulum system.

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Analysis of parallel manipulators with redundant limbs (잉여 다리 병렬형 로봇의 해석)

  • 김성복
    • 제어로봇시스템학회:학술대회논문집
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    • 1996.10b
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    • pp.730-733
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    • 1996
  • This paper presents the kinematic and dynamic analysis of parallel manipulators with redundant limbs, obtained by putting additional limbs to an existing parallel manipulator. We develop the kinematic and dynamic models of a parallel, manipulator with redundant limbs. The redundancy in parallelism due to the increased number of limbs and the redundancy in actuation due to the increased number of active joints are considered in the modeling. Based on the derived models, we define the kinematic and dynamic manipulabilities of a parallel manipulator with redundant limbs. The effect of the redundant limbs on the performance of parallel manipulators is analyzed in terms of kinematic and dynamic manipulabilities.

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Organization of Parallelizing Compilers (병렬화 컴파일러의 구조)

  • Lee, J.K.;Chi, D.;Chang, B.-M.
    • Electronics and Telecommunications Trends
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    • v.9 no.4
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    • pp.9-21
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    • 1994
  • Wide variety of the architectural complexity of parallel computer often makes it difficult to develop efficient programs for them. One of approaches to improve this difficulty is to program in familiar sequential languages such as Fortran or C and to parallelize sequential programs into equivalent parallel programs automatically. This paper presents an organization of parallelizing compiler which transforms sequential programs into equivalent parallel programs. The parallelizer consists mainly of syntax analysis, control and data flow analysis, program transformation, and parallel code generation. In particular, the program restructuring in this parallelizer maximizes loop parallelism.

Evolutionay Robotics based on Interactive Technology (인터액티브 테크놀로지와 진화로봇)

  • 윤중선
    • 제어로봇시스템학회:학술대회논문집
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    • 2000.10a
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    • pp.530-530
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    • 2000
  • A new paradigm of technology, based on the overall interactions of technology, humans and environment through Korperlichkeit(corporeality or philosophy of Mom), is explored. Parallelism based on holism and embodiment, and relative interactions based on correspondence and interrelationships, are the key ideas in the proposed paradigm. Biological information processing systems much resemble the key ideas of interactive technology. Robots could be easily implemented from this evolutionary engineering approach.

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Implementation of DCT using Bit Slice Signal Processor (BIT SLICE SIGNAL PROCESSOR를 이용한 DCT의 구현)

  • Kim, Dong-L.;Go, Seok-B.;Paek, Seung-K.;Lee, Tae-S.;Min, Byong-G.
    • Proceedings of the KIEE Conference
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    • 1987.07b
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    • pp.1449-1453
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    • 1987
  • A microprogrammable Bit Slice Sinal Processor for image processing is implemented. Processing speed is increased by the parallelism in horizontal microprogram using 120bits microcode, pipelined architecture, 2 bank memory switching that interfaces with the Host through DMA, a variable clock control, overflow checking H/W,look-up table method and cache memory. With this processor, a DCT algorithm which uses 2-D FFT is performed. The execution time for $512{\times}512{\times}8$ image is 12 sec when 16 bit operation is runned, and the recovered image has acceptable quality with MSE 0.276%.

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A Study on the Neuro-Fuzzy Control and Its Application

  • So, Myung-Ok;Yoo, Heui-Han;Jin, Sun-Ho
    • Journal of Advanced Marine Engineering and Technology
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    • v.28 no.2
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    • pp.228-236
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    • 2004
  • In this paper. we present a neuro-fuzzy controller which unifies both fuzzy logic and multi-layered feed forward neural networks. Fuzzy logic provides a means for converting linguistic control knowledge into control actions. On the other hand. feed forward neural networks provide salient features. such as learning and parallelism. In the proposed neuro-fuzzy controller. the parameters of membership functions in the antecedent part of fuzzy inference rules are identified by using the error back propagation algorithm as a learning rule. while the coefficients of the linear combination of input variables in the consequent part are determined by using the least square estimation method. Finally. the effectiveness of the proposed controller is verified through computer simulation for an inverted pole system.

Performance Improvement of Single Chip Multiprocessor using Concurrent Branch Execution (분기 동시 수행을 이용한 단일 칩 멀티프로세서의 성능 개선)

  • Lee, Seung-Ryul;Kim, Jun-Shik;Choi, Jae-Hyeok;Choi, Sang-Bang
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.2
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    • pp.61-71
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    • 2007
  • The instruction level parallelism, which has been used to improve the performance of processors, expose its limit. The change of a control flow by a branch miss prediction is one of the obstacles that restrict the instruction level parallelism. The single chip multiprocessors have been developed to utilize the thread level parallelism. However, we could not use the maximum performance of the single chip multiprocessor in case of executing the coded programs without considering the multi-thread. In order to overcome the two performance degradation factors, in this paper, we suggest the concurrent branch execution method that applies to the multi-path execution method at a single chip multiprocessor. We executes all two flows of the conditional branch using the idle core processor. Through this, we can improve the processor's efficiency with blocking the control flow termination by the branch instruction and reducing the idle time. We analyze the effects of concurrent branch execution proposed in this paper through the simulation. As a result of that, concurrent branch execution reduces about 20% of idle time and improves the maximum 10% of the branch prediction accuracy. We show that our scheme improves the overall performance of maximum 39% compared to the normal single chip multiprocessor and maximum 27% compared to the superscalar processor.

Study of an In-order SMT Architecture and Grouping Schemes

  • Moon, Byung-In;Kim, Moon-Gyung;Hong, In-Pyo;Kim, Ki-Chang;Lee, Yong-Surk
    • International Journal of Control, Automation, and Systems
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    • v.1 no.3
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    • pp.339-350
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    • 2003
  • In this paper, we propose a simultaneous multithreading (SMT) architecture that improves instruction throughput by exploiting instruction level parallelism (ILP) and thread level parallelism (TLP). The proposed architecture issues and completes instructions belonging to the same thread in exact program order. The issue and completion policy greatly reduces the design complexity and hardware cost of our architecture, compared with others that employ out-of-order issue and completion. On the other hand, when the instructions belong to different threads, the issue and completion orders for those instructions may not necessarily be identical to the fetch order. The processor issues instructions simultaneously from multiple threads to functional units by exploiting ILP and TLP, and by dynamic resource sharing. That parallel execution notably improves performance and resource utilization with minimal additional hardware cost over the conventional superscalar processors. This paper proposes an SMT architecture with grouping as well as one without grouping. Without grouping, all threads dynamically and flexibly share most resources. On the other hand, in the SMT architecture with grouping, in which resources and threads are divided into several groups for design simplification, resources are shared only among threads belonging to the same group as those resources. Simulation results show that our processors with four and eight threads improve performance by three or more times over the conventional superscalar processor with comparable execution resources and policies, and that reasonable grouping reduces the design complexity of SMT processors with little negative effect on performance.