• Journal of the Korean Society for Industrial and Applied Mathematics
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• v.24 no.2
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• pp.199-214
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• 2020

This paper describes the development of a parallel computational algorithm based on the finite element tearing and interconnecting (FETI) method that uses a local Lagrange multiplier. In this approach, structural computational domain is decomposed into non-overlapping sub-domains using local Lagrange multiplier. The local Lagrange multipliers are imposed at interconnecting nodes. 8-node solid element using extra shape function is adopted by using the representative volume element (RVE). The parallel computational algorithm is further established based on message passing interface (MPI). Finally, the present FETI-local approach is implemented on parallel hardware and shows improved performance.

• The Transactions of the Korea Information Processing Society
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• v.6 no.3
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• pp.792-803
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• 1999

Most data parallel language compilers are source-to-source translators. Most Compilers of HPF which is recognized as a standard data parallel language convert a parallel program in PHF in a Fortran 77 program inserted message passing primitives. By the way, they currently generate significant amount of ineffective codes in the course of the conversion. Especially, FORALL construct is converted into several DO loops, so loop overhead of these codes is very increased. In this paper, we define and use relation distance vector to keep necessary informations. Then we evaluate and analyze execution time for the codes converted by our method and by PARADIGM method for various array sizes.

• Nuclear Engineering and Technology
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• v.53 no.11
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• pp.3643-3652
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• 2021

Sizing the tube inlet orifice of a Once-Through Steam Generator (OTSG) is important to protect the integrity of the tubes from thermal cycling and vibration wear. In this study, a new sizing criterion is proposed for the tube inlet orifice to suppress the parallel channel instability in an OTSG. A perturbation method is used to capture the essential parts of the thermal-hydraulic phenomena of the parallel channel instability. The perturbation model of the heat transfer regime boundaries is identified as a missing part in existing models for sizing the OTSG tube inlet orifice. Limitations and deficiency of the existing models are identified and the reasons for the limitations are explained. The newly proposed model can be utilized to size the tube inlet orifice to suppress the parallel channel instability without excessive engineering margin.

• Progress in Superconductivity and Cryogenics
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• v.10 no.1
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• pp.32-36
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• 2008

An HTS conductor with parallel HTS tapes is essential for a large power HTS device to flow a large current. One of the most important factor for this conductor is a current distribution. Non-uniform current distribution in parallel tapes makes the critical current of the conductor low and the AC losses high. In this paper we proposed a non-contact method which measured each current in parallel tapes by using an array of Hall sensors. A matrix can be derived from this array for calibration. The current distributions of 4 and 6 parallel tapes were measured.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.13 no.3
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• pp.44-52
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• 2004

This paper proposed a error compensation methodology for three-DOF translational parallel manipulator. The proposed method uses CMM (coordinate measuring machine) as metrology equipment to measure the position of end-effector. To identify the transform relationships between the coordinate system of the parallel manipulator and the CMM coordinate system, a new coordinate referencing (or coordinate system identification) technique is presented. By using this technique, accurate coordinate transformation relationships are efficiently established. According to these coordinate transformation relationships, an equation to calculate the compensating error components at any arbitrary position of the end-effector is derived. In this paper, Monte Carlo simulation method is applied to simulate the compensation process. Through the simulation results, the proposed error compensation method proves its effectiveness and feasibility.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.13-16
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• 2005

It would be desirable to have methods for specific problems, which have low communication costs compared to the computation costs, and in specific applications, algorithms need to be developed and mapped onto parallel computer architectures. Main memory access for shared memory system or global communication in message passing system deteriorate the computation speed. In this paper, it is found that the m-step generalization of the block Lanczos method enhances parallel properties by forming m simultaneous search direction vector blocks. QR factorization, which lowers the speed on parallel computers, is not necessary in the m-step block Lanczos method. The m-step method has the minimized synchronization points, which resulted in the minimized global communications compared to the standard methods.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2000.06a
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• pp.743-750
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• 2000

This paper presents an equivalent linearization method and application to the equations of motion of a 6 degree-of-freedom PRRS HexaSlide type parallel manipulators which are characterized as the architecture with constant link lengths that are attached to moving sliders on the ground and to a mobile platform. Since dynamic equations of parallel manipulators are complicated and highly nonlinear, control bandwidth, adjustable control gain as well as vibration characteristics cannot be easily found. The proposed equivalent linearization method can be applied over specified workspace as well as on a path of mobile platform. Through an equivalent linearization method, one can easily get a simple linear dynamic model. This linearized dynamic model may be utilized in a simplified computed torque control strategy.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.2
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• pp.189-196
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• 1994

This paper describes a parallel computing algorithm in Gauss elimination of Jacobian matrix to large-scale power system. The structure of Jacobian matrix becomes different according to ordering method of buses. In sequential computation buses are ordered to minimize the number of fill-in in the triangulation of the Jacobian matrix. The proposed method develops the parallelism in the Gauss elimination by using ND(nested dissection) ordering. In this procedure the level structure of the power system network is transformed to be long and narrow by using end buses which results in balance of computing load among processes and maximization of parallel computation. Each processor uses the sequential computation method to preserve the sqarsity of matrix.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.9
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• pp.4349-4371
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• 2019

Moldable parallel tasks are widely used in different areas, such as weather forecast, biocomputing, mechanical calculation, and so on. Considering the deadline and the speedup, scheduling moldable parallel tasks becomes a difficulty. Past work majorly focuses on the LA (List Algorithms) or OMA (Optimizing the Middle Algorithms). Different from prior work, our work normalizes execution time and makes all tasks have the same scope in normalized execution time: [0,1], and then according to the normalized execution time, a method is used to search for the reference execution time without considering the deadline of tasks. According to the reference execution time, we get an initial scheduling result based on AFCFS (Adaptive First Comes First Served) policy. Finally, a heuristic approach is used to improve the performance of the initial scheduling result. We call our method HSRET (a Heuristic Scheduling method based on Reference Execution Time). Comparisons to other methods show that HSRET has good performance in AWT (Average Waiting Time), AET (Average Execution Time), and PUT (Percentages of Unfinished Tasks).

• Journal of the Korean Society of Industry Convergence
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• v.24 no.1
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• pp.69-77
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• 2021

The widely used low-cost design methodology for IoT devices is very popular. In such a networked device, memory is composed of flash memory, SRAM, DRAM, etc., and because it processes a large amount of data, memory design is an important factor for system performance. Therefore, each device selects optimized design factors such as function, performance and cost according to market demand. The design of a memory architecture available for low-cost IoT devices is very limited with the configuration of SRAM, flash memory, and DRAM. In order to process as much data as possible in the same space, an architecture that supports parallel processing units is usually provided. Such parallel architecture is a design method that provides high performance at low cost. However, it needs precise software techniques for instruction and data mapping on the parallel architecture. This paper proposes an instruction/data mapping method to support optimized parallel processing performance. The proposed method optimizes system performance by actively using hardware and software parallelism.