• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.2
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• pp.355-361
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• 1987

The shuffle-exchange graph is known as a structure to perform the parallel algorithms like Discrete Fourier Transform(DFT), matrix multiplication and sorting. In this paper, the layout for the shuffle-exchange graph is described and this layout places emphasis on the placement of nodes that has the capability to have as small area as possible, have as a small number of crossings as possible, and have as short wires as possible. The algorithm corrdsponding these conditions is proposed and each evaluation factor and the placement of the N-node shuffle-exchange graph is performed with FORTRAN and BASIC program, and these results are calcualted.

• Journal of the Korean Institute of Educational Facilities
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• v.23 no.1
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• pp.43-54
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• 2016

The purpose of this study was to survey teachers' perception of classroom space utilization through analyzing the physical environment of elementary school classrooms (56 classrooms in 10 schools). Most of the teachers arranged desks in the two person parallel type (sectional layout : standard type) for their classes. Although the number was small, some classrooms used the T type, H type, U type, group type, and the teachers of such cases used these layouts for children's play activities or group learning. Some teachers changed the desk layout depending on the contents of learning or for different atmosphere of class, but about 40% of the teachers used the same classroom layout without any change during a semester. When the teachers' perception of classroom space utilization was examined according to the type and change of desk layout, the quantity and characteristics of posts, the position of posting spaces, and the size of activity spaces in the classroom, most of the teachers tended to be conventional without any characteristic, and only 16% of them were relatively active in utilizing classroom spaces. In addition, teachers of a relatively small class were more active in utilizing classroom spaces. In particular, perception was very low to utilize the classroom as a space for children's life or play activities or various types of learning. These findings suggest that it is necessary to improve teachers' perception of classroom space utilization in the future.

• Journal of Korean Tunnelling and Underground Space Association
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• v.5 no.1
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• pp.55-70
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• 2003

Ammunition magazine, which is installed on the ground, has difficulty in protecting from the external attack, and accidental explosion should cause great damage to the life and property. For these reasons, it is needed to develop underground magazine that it has the advantages of safety, security and maintenance. This paper introduce the design case for blasting facilities, which should resist blasting pressure, as well as layout of underground magazine, which takes a safety for explosion and a working space of loading/unloading machine into consideration. On the layout, in case of ${\bigcirc}{\bigcirc}$ underground magazine, put three storage chambers in position almost parallel with principle stress direction, where less effected on discontinuity and hard rock area. Also, secured safe distance according to safety criteria of the Defense Ministry, and verified suitable layout by trace simulation for loading/unloading machine on working stage. Blasting design was performed on evaluation of maximum blast pressure between donar and acceptor chambers, and design condition for blast door, valve, etc. Diminution facilities against explosion, such as thrust block or debris trap, determined its size after plan in accordance with blasting criteria and calculation by structural analysis.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.1
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• pp.8-15
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• 1993

A concrete disign of memory circuit is presented aiming at the application of sliding diagonal test patterns. A modification of sliding diagonal test pattern includes the complexity reduction from O(n$^{32}$) to O(n) using parallel test memory concept. The control circuit design was based on delay-element, and verified via logic and circuit simulation. Area overhead was evaluated based on physical layout using a 0.7 micron design rule resulting in about 1% area increase for a typical 16Mbit DRAM.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.6
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• pp.1056-1063
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• 1994

In this paper a content addressable memory (CAM) is designed by adopting best-match method. It has a single processing element(PE) architecture with high computational efficiency and throughput. It is composed of three main functional blocks(input MUX, best-match CAM, control part). It support fully parallel processing. Logic simulation is completed by using QUICKSIM, Circuit simulation is performanced by using HSPICE. Its layout is based on the ETRI 3 m n-well process design rules. Its maximum operating frequency is 20 MHz.

• Journal of the Society of Naval Architects of Korea
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• v.47 no.1
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• pp.58-66
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• 2010

Topology design optimization is a method to determine the optimal distribution of material that yields the minimal compliance of structures, satisfying the constraint of allowable material volume. The method is easy to implement and widely used so that it becomes a powerful design tool in various disciplines. In this paper, a large-scale topology design optimization method is developed using the efficient adjoint sensitivity and optimality criteria methods. Parallel computing technique is required for the efficient topology optimization as well as the precise analysis of large-scale problems. Parallelized finite element analysis consists of the domain decomposition and the boundary communication. The preconditioned conjugate gradient method is employed for the analysis of decomposed sub-domains. The developed parallel computing method in topology optimization is utilized to determine the optimal structural layout of human powered vessel.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.121-126
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• 2007

This paper describes a 9.09 Gb/s CMOS demultiplexer using redundant multi-valued logic (RMVL). The proposed circuit receives serial binary data and is converted to parallel redundant multi-valued data using RMVL. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. Each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The demultiplexer is designed with Samsung $0.35{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the post layout simulation. The demultiplexer is achieved the maximum data rate of 9.09 Gb/s and the average power consumption of 69.93 mW. This circuit is expected to operate at higher speed than 9.09 Gb/s in the deep-submicron process of the high operating frequency.

• Geomechanics and Engineering
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• v.29 no.2
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• pp.145-154
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• 2022

Complex geological conditions have a great influence on the mining of coalbed methane (CBM), which affects the extraction efficiency of CBM. This investigation analyzed the complicated geological conditions in the Liujia CBM block of Fuxin. A geological model of heterogeneities CBM reservoirs was established to study the influence of strike direction of igneous rocks and fault structures on horizontal well layout. Subsequently, the dual-porosity and dual-permeability mathematical model was established, which considers the dynamic changes of porosity and permeability caused by gas adsorption, desorption, pressure change. The results show that the production curve is in good agreement with the actual by considering gas seepage in matrix pores in the model. Complicated geological structures affect the pressure expansion of horizontal wells, especially, the closer to the fault structure, the more significant the effect, the slower the pressure drop, and the smaller the desorption area. When the wellbore extends to the fault, the pressure expansion is blocked by the fault and the productivity is reduced. In the study area, the optimal distance to the fault is 70 m. When the horizontal wellbore is perpendicular to the direction of coal seam igneous rock, the productivity is higher than that of parallel igneous rock, and the horizontal well bore should be perpendicular to the cleat direction. However, the well length is limited due to the dense distribution of igneous rocks in the Liujia CBM block. Therefore, the horizontal well pumping in the study area should be arranged along the direction of igneous rock and parallel plane cleats. It is found that the larger the area surrounded by igneous rock, the more favorable the productivity. In summary, the reasonable layout of horizontal wells should make full use of the advantages of igneous rock, faults and other complex geological conditions to achieve the goal of high and stable production.

• The KIPS Transactions:PartA
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• v.9A no.2
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• pp.259-266
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• 2002

In this paper we implemented various image processing filtering using the format converter. This design method is based on realized the large processor-per-pixel array by integrated circuit technology. These two types of integrated structure are can be classify associative parallel processor and parallel process DRAM (or SRAM) cell. Layout pitch of one-bit-wide logic is Identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start. As a result, we obtained three result that 1) simple smoothing suppresses higher spatial frequencies, reducing noise but also blurring edges, 2) a smoothing and segmentation process reduces noise while preserving sharp edges, and 3) median filtering may be applied to reduce image noise. Median filtering eliminates spikes while maintaining sharp edges and preserving monotonic variations in pixel values.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.3
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• pp.6-15
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• 2000

In this paper, we propose a high speed parallel multiplier with a hierarchical architecture using a fast 4-2 compressor and 6-2 compressor. Generally, the performance of parallel multiplier depends on the processing speed of partial products summation tree with CSA adder. In this paper we propose a new circuit of 4-2 compressor and 6-2 compressor which reduces the propagation delay time, compared with conventional one. We Propose a hierarchical multiplier architecture in order to improve the execution speed of 16$\times$16 parallel multiplier using proposed compressors in this paper and make layout design easily by regular structure. The propagation delay time of the proposed 4-2 compressor circuit was 14% reduced as a result of SPICE simulation, compared with the conventional 4-2 compressor. The total propagation delay time of proposed 16$\times$16 parallel multiplier was 12% reduced using proposed 4-2 compressor and 6-2 compressor.