• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.45-53
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• 2006

In this paper, we proposed a parallel hardware architecture for deblocking filter in K264/AVC. The deblocking filter has high efficiency in H.264/AVC, but it also has high computational complexity. For real time video processing, we chose a two 1-D parallel filter architecture, and tried to reduce memory access using dual-port SRAM. The proposed architecture has been described in Verilog-HDL and synthesized on Hynix 0.25um CMOS Cell Library using Synopsys Design Compiler. The hardware size was about 27.3K logic gates (without On-chip Memory) and the maximum operating frequency was 100Mhz. It consumes 258 clocks to process one macroblock, witch means it can process 47.8 HD1080P(1920pixel* 1080pixel) frames per second. It seems that it can be used for real time H.264/AVC encoding and decoding of various multimedia applications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.11C
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• pp.901-906
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• 2010

Low density parity check (LDPC) code, first introduced by Gallager and re-discovered by MacKay et al, has attracted researcher's interest mainly due to their performance and low decoding complexity. It was remarkable that the performance is very close to Shannon capacity limit under the assumption of having long codeword length and iterative decoder. However, comparing to turbo codes widely used in the current mobile communication, the encoding complexity of LDPC codes has been regarded as the drawback. This paper proposes a solution for DVB-S2 LDPC encoder to reduce the encoder latency. We use the fast IRA encoder that use the transformation of the parity check matrix into block-wise form and the partial parallel process to reduce the number of system clocks for the IRA code encoding. We compare the proposed encoder with the current DVB-S2 encoder to show that the performance of proposal is better than that of the current DVB-S2 encoder.

• MALSORI
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• no.52
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• pp.111-120
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• 2004

This paper focuses on the DSP implementation of an HMM-based speech recognizer that can handle several hundred words of vocabulary size as well as speaker independency. First, we develop an HMM-based speech recognition system on the PC that operates on the frame basis with parallel processing of feature extraction and Viterbi decoding to make the processing delay as small as possible. Many techniques such as linear discriminant analysis, state-based Gaussian selection, and phonetic tied mixture model are employed for reduction of computational burden and memory size. The system is then properly optimized and compiled on the TMS320C6711 DSP for real-time operation. The implemented system uses 486kbytes of memory for data and acoustic models, and 24.5 kbytes for program code. Maximum required time of 29.2 ms for processing a frame of 32 ms of speech validates real-time operation of the implemented system.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.1
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• pp.28-34
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• 2015

Several parallelization methods that can be applied to High Efficiency Video Coding (HEVC) decoders are evaluated. The market requirements of high-resolution videos, such as Full HD and UHD, have been increasing. To satisfy the market requirements, several parallelization methods for HEVC decoders have been studied. Understanding these parallelization methods and objective comparisons of these methods are crucial to the real-time decoding of high-resolution videos. This paper introduces the parallelization methods that can be used in HEVC decoders and evaluates the parallelization methods comparatively. The experimental results show that the average speed-up factors of tile-level parallelism, wavefront parallel processing (WPP), frame-level parallelism, and 2D-wavefront parallelism are observed up to 4.59, 4.00, 2.20, and 3.16, respectively.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2011.07a
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• pp.396-398
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• 2011

본 논문은 두 대의 카메라와 한 대의 프로젝터로 구성된 Pro-cam시스템을 이용하여, 출력된 패턴 영상을 카메라로 촬영하고 이를 기반으로 Depth Map을 계산하는 모듈의 실시간 처리를 위한 GPU기반 병렬처리 기법을 제안한다. 입력받은 영상으로부터 구조광의 패턴을 해석하고, Depth Map을 계산하기 위해서, Dynamic pattern decoding하는 과정은 프로젝터의 패턴영상과 촬영된 카메라 패턴영상 간의 관계를 반복적으로 비교하므로, 이를 GPU 프로그래밍을 이용하여 병렬 처리를 통해 고속화하였다. 결과적으로 본 논문에서는 기존 CPU에서 수행했던 속도에 비해 약 18배정도 속도를 개선 할 수 있었다.

• Journal of Communications and Networks
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• v.16 no.3
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• pp.249-257
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• 2014

This paper presents methods to the construction of regular and irregular low-density parity-check (LDPC) codes based on Euclidean geometries over the Galois field. Codes constructed by these methods have quasi-cyclic (QC) structure and large girth. By decomposing hyperplanes in Euclidean geometry, the proposed irregular LDPC codes have flexible column/row weights. Therefore, the degree distributions of proposed irregular LDPC codes can be optimized by technologies like the curve fitting in the extrinsic information transfer (EXIT) charts. Simulation results show that the proposed codes perform very well with an iterative decoding over the AWGN channel.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.155-164
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• 1996

The architecture of a programmable video codec IC is described that employs multiple vector processors in a single chip. The vector processors operate in parallel and communicate with one another through on-chip shared memories. A single scalar control processor schedules each vector processor independently to achieve real-tiem video coding with special vector instructions. With programmable interconnection buses, the proposed architecture performs multi-processing of tasks and data in video coding. Therefore, it can provide good parallelism as well as good programmability. especially, it can operate multithread video coding, which processes several independent image sequences simultaneously. We explain its scheduling, multithred video coding, and vector processor architectures. We implemented a prototype video codec with a 0.8um CMOS cell-based technology for the multi-standard videophone. This codec can execute video encoding and decoding simultaneously for the QCIF image at a frame rate of 30Hz.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.2271-2272
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• 2008

Recently, LDPC codes received a lot of attention in 4G. LDPC codes perform good error correction at high SNR. But LDPC codes are complex design and not good at low SNR. At low SNR, convolution codes and turbo codes show more good performance than LDPC codes. The main subject presented in this study is that parallel encoding and decoding according to SNR. The system chooses convolution codes at low SNR and chooses LDPC codes at high SNR.

• Journal of electromagnetic engineering and science
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• v.4 no.1
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• pp.17-22
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• 2004

In this paper, we implement an efficient MLC/PDL system for AWGN channels. In terms of the tradeoff between the hardware implementation and system performance, proposed algebra LDPC codes are optimized by the Gaussian approximation(GA) according to the rate of each level assigned by the capacity rule and chosen as the component code. System performance with Ungerboeck Partitioning(UP), Miked Partitioning(MP) and Gray Mapping(GM) of 8PSK are evaluated, respectively. Many results are presented in this paper; they can indicate that the proposed MLC/PDL system using optimized algebra LDPC codes with different code rate, capacity rule and Gray mapping(GM) can achieve the best performance.

• Journal of the Korean Operations Research and Management Science Society
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• v.28 no.2
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• pp.1-15
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• 2003

This paper presents a new evolutionary algorithm to solve complex multi-level integration problems, which is called multi-level symbiotic evolutionary algorithm (MEA). The MEA uses an efficient feedback mechanism to flow evolution information between and within levels, to enhance parallel search capability, and to improve convergence speed and population diversity. To show the MEA's applicability, It is applied to the integrated planning of production and distribution in supply chain management. The encoding and decoding methods are devised for the integrated problem. A set of experiments has been carried out, and the results are reported. The superiority of the algorithm's performance is demonstrated through experiments.