• Journal of KIISE:Computing Practices and Letters
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• v.8 no.3
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• pp.251-260
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• 2002

The parallel/distributed processing with a lot of the idle hosts on the web has the high coot-performance ratio for large-scale applications. It's processing has to show the solutions for unpredictable status such as heterogeneity of hosts, variability of hosts, autonomy of hosts, the supporting performance continuously, and the number of hosts which are participated in computation and so on. In this paper, we propose the strategy of adaptive tack reallocation based on performance the host job processing, spread out geographically Also, It shows the scheme of dynamic host management with dynamic environment, which is changed by lots of hosts on the web during parallel processing for large-scale applications. This paper implements the PDSWeb (Parallel/Distributed Scheme on Web) system, evaluates and applies It to the generation of rendering image with highly intensive computation. The results are showed that the adaptive task reallocation with the variation of hosts has been increased up to maximum 90% and the improvement in performance according to add/delete of hosts.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.480-483
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• 1997

A fossil power plant can be modeled by a lot of algebraic equations and differential equations. When we simulate a large, complicated fossil power plant by a computer such as workstation or PC, it takes much time until overall equations are completely calculated. Therefore, new processing systems which have high computing speed is ultimately needed to develope real-time simulators. Vital points of real-time simulators are accuracy, computing speed, and deadline observing. In this paper, we present a enhanced strategy in which we can provide powerful computing power by parallel processing of DSP processors with communication links. We designed general purpose DSP modules, and a VME interface module. Because the DSP module is designed for general purpose, we can easily expand the parallel system by just connecting new DSP modules to the system. Additionally we propose methods about downloading programs, initial data to each DSP module via VME bus, DPRAM and processing sequences about computing and updating values between DSP modules and CPU30 board when the simulator is working.

• Journal of the Korea Society of Computer and Information
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• v.18 no.1
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• pp.1-10
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• 2013

In this paper, we propose a CUDA(Common Unified Device Architecture) based SW(software) design method for CPU(Central Processing Unit) and GPU(Graphic Processing Unit) parallel structure to implement real-time process in 3D Laser ladar(LADAR) imaging system. LADAR is a complex system to generate 3-dimensional image based on the laser ranging information, and requires massive process resources in each phase. Therefore, designing and implementing parallel structure are crucial to realize a real-time process within limited system resource. As a conclusion, we can meet the speed of required real-time process allocating separable work load to CUDA GPU by analyzing process algorithm in each phase and confirm the process speed increase by 46%.

• The Transactions of the Korea Information Processing Society
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• v.2 no.2
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• pp.148-155
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• 1995

When we analize many amount of patterns, it is necessary for these patterns are to be clustering into several groups according to a certain evaluation function. This process, in case that there are lots of input patterns, needs a considerable amount of computations and is reqired parallel algorithm for these. To solve this problem, this paper propose parallel clustering algorithm which parallelized k-means algorithm and implemented it under the MIMD parallel computer based message passing. The result is through the experiment and performance analysis, that this parallel algorithm is appropriate in case these are many input patterns.

• Journal of Information Processing Systems
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• v.13 no.1
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• pp.104-113
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• 2017

In this paper, we present an approach to transmit data from the source to the destination through a minimal path (least-cost path) in a computer network of n nodes. The motivation behind our approach is to address the problem of finding a minimal path between the source and destination. From the work we have studied, we found that a Steiner tree with bounded Steiner vertices offers a good solution. A novel algorithm to construct a Steiner tree with vertices and bounded Steiner vertices is proposed in this paper. The algorithm finds a path from each source to each destination at a minimum cost and minimum number of Steiner vertices. We propose both the sequential and parallel versions. We also conducted a comparative study of sequential and parallel versions based on time complexity, which proved that parallel implementation is more efficient than sequential.

• Journal of Advanced Information Technology and Convergence
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• v.9 no.2
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• pp.89-97
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• 2019

Recently, there is an increasing demand for applications utilizing maps and locations such as autonomous vehicles and location-based services. Since these applications are developed based on spatial data, interest in spatial data processing is increasing and various studies are being conducted. In this paper, I propose a parallel mining algorithm using the CUDA library to efficiently analyze large spatial data. Spatial data includes both geometric (spatial) and non-spatial (aspatial) attributes. The proposed parallel spatial data mining algorithm analyzes both the geometric and non-spatial relationships between two layers. The experiment was performed on graphics cards containing CUDA cores based on TIGER/Line data, which is the actual spatial data for the US census. Experimental results show that the proposed parallel algorithm using CUDA greatly improves spatial data mining performance.

• Electronics and Telecommunications Trends
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• v.4 no.1
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• pp.93-117
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• 1989

Computational Geometry is concerned with the design and analysis of computational algorithms which solve geometry problems. Geometry problems have a large number of applications areas such as pattern recognition, image processing, computer graphics, VLSI design and statistics since they involve inherently geometric problems for which efficient algorithms have to be developed. Several parallel algorithms, based on various parallel computation models, have been proposed for solving geometric problems. We review the current status of the parallel algorithms in computational geometry.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.4
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• pp.38-49
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• 1998

A fossil power plant can be modeled by a lot of algebraic equations and differential equations. When we simulate a large, complicated fossil power plant by a computer such as workstation or PC, it takes much time until overall equations are completely calculated. Therefore, new processing systems which have high computing speed is ultimately needed for real-time or high-speed(faster than real-time) simulators. This paper presents an enhanced strategy in which high computing power can be provided by parallel processing of DSP processors with communication links. DSP system is designed for general purpose. Parallel DSP system can be easily expanded by just connecting new DSP modules to the system. General urpose DSP modules and a VME interface module was developed. New model and techniques for the task allocation are also presented which take into account the special characteristics of parallel I/O and computation. As a realistic cost function of task allocation, we suggested 'simulation period' which represents the period of simulation output intervals. Based on the development of parallel DSP system and realistic task allocation techniques, we cound achieve good efficiency of parallel processing and faster simulation speed than real-time.

• Journal of the Korea Society of Computer and Information
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• v.19 no.7
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• pp.9-16
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• 2014

Since the haze removal algorithm using dark channel prior was introduced, many researches for improving processing speed have been addressed even if it presented impressive results. Remarkable one is using median dark channel prior. Although it has been considered as a very attactive method, processing speed is as low as ever. So, a parallel memory model which is suitable for SIMD architecture processing haze removal on high-definition images in high-speed is introduced in this paper. The proposed parallel memory model allows to access n pixels simultaneously. It is also support stride 3, 5, 7, and 11 in order to execute convolution mask operations, e.g., median filter. The proposed parallel memory model can therefore support enough data bandwidth to process the algorithm using median dark channel prior in high-speed.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.409-410
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• 2008

This paper presents nonlinear and parallel design for synchronous pipelining in IP-based H.264 decoder implementation. Since H.264 decoder includes the dataflow of feedback loop, the data dependency requires one NOP stage per pipelining latency to drop the throughput into 1/2. Further, it is found that, in execution time, the stage scheduled for MC is more occupied than that for CAVLD/ITQ/DF. The less efficient stage would be improved by nonlinear scheduling, while the fully-utilized stage could be accelerated by parallel scheduling of IP. The optimization yields 3 nonlinear {CAVLD&ITQ}|3 parallel (MC/IP&Rec.)| 3 nonlinear {DF} pipelined architecture for IP-based H.264 decoder. In experiments, the nonlinear and parallel pipelined H.264 decoder, including existing IPs, could deal with full HD video at 41.86MHz, in real time processing.