• Proceedings of the Korea Information Processing Society Conference
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• 2006.05a
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• pp.743-746
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• 2006

In this paper, we propose and analyze a new parallel computer topology, called the Fibonacci posterorder circulants. It connects ${\Large f}_x,\;n{\geq}2$ processing nodes, same the number of nodes used in a comparable Fibonacci cube. Yet its diameter is only ${\lfloor}\frac{n}{3}{\rfloor}$ almost one third that of the Fibonacci cube. Fibonacci cube is asymmetric, but it is a regular and symmetric static interconnection networks for large-scale, loosely coupled systems. It includes scalability and Fibonacci cube as a spanning subgraph.

• Proceedings of the Korea Information Processing Society Conference
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• 2016.04a
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• pp.59-60
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• 2016

본 논문에서는 고성능 병렬 계산 장치로 주목받고 있는 GPU를 CPU와 동시에 병렬로 사용한 계산 성능을 분석하였다. 성능 분석을 위하여 원주율(${\pi}$)을 적분으로 계산하는 CUDA 프로그램을 사용하였으며, 전체 계산을 GPU 대비 CPU 계산 부분으로 할당하여 성능을 분석하였다.

• Proceedings of the Korean Society of Computer Information Conference
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• 2010.07a
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• pp.513-514
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• 2010

• Journal of Advanced Marine Engineering and Technology
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• v.34 no.6
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• pp.858-863
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• 2010

In order to enhance encoding speed in dynamic image encoding using H.264/AVC, reducing the time for motion estimation which takes a large portion of the processing time is very important. An approach using graphics processing unit(GPU) as a coprocessor to assist the central processing unit(CPU) in computing massive data, will be a way to reduce the processing time. In this paper, we present an efficient block-level parallel algorithm for the motion estimation(ME) on a computer unified device architecture(CUDA) platform developed in general-purpose computation on GPU. Experiments are carried out to verify the effectiveness of the proposed algorithm.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04a
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• pp.357-360
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• 2002

본 논문에서는 고장 노드를 갖는 $n{\times}k$ 토러스(Torus)가 Strong Fault-Tolerance글 가짐을 보인다$(n{\geq}k)$. 또한 그 결과를 이용하여 $n{\times}k$ 토러스(Torus)에서 분지수-2, 즉 2개의 고장노드 발생시 임의의 두 노드 사이에 병렬경로 길이가 n+2 이하임을 보인다.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.11a
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• pp.1457-1460
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• 2013

We propose a flexible camera calibration system for mobile platform to calibrate the camera's intrinsic parameters which based on the geometrical property of the vanishing points determined by two perpendicular groups of parallel lines. The system only requires the camera to observe a rectangle card show at a few(at least four)different orientation. The experimental results of the real images show the proposed calibration system in this paper is easy to use and robust.

• Journal of the Korea Computer Industry Society
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• v.7 no.3
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• pp.185-190
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• 2006

In this paper, a simple parallel compiler using of Parafrase II is presented. This is a new general method the extracting parallelism in order to parallel processing effectively in nested loop. For this, the source program of Parafrase II parallel compiler is analyzed and implemented. Moreover, this method can be applicable where the dependency relation is both uniform and non-uniform in distance.

• Journal of the Korea Computer Industry Society
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• v.3 no.8
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• pp.981-988
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• 2002

In this paper, a simple parallel compiler of a sequential loop is presented. This is a procedure for the automatic conversion of a sequential loop into a nested parallel DOALL loops at compile time. For this. the source program of Parafrase II parallel compiler is analyzed and a new general method the extracting parallelism in order to parallel processing effectively in nested loop is implemented.

• Journal of the Korea Computer Industry Society
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• v.9 no.2
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• pp.63-68
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• 2008

The purpose of a parallel scheduling is to carry out the scheduling with the minimum synchronization overhead and bottleneck under a multiprocessor environment and to perform load balance for a parallel iteration. In this paper, analyse the conventional parallel scheduling methods and drive the problems from each method in order to achive the minimum scheduling overhead and load balance. These problems will go far toward solving the design of effective algorithm.

• Proceedings of the Korea Inteligent Information System Society Conference
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• 2006.06a
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• pp.303-310
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• 2006

The sorting algorithms have been developed to take advantage of distributed computers. But the speedup of parallel sorting algorithms decrease rapidly with increased number of processors due to parallel processing overhead such as context switching time and inter-processor communication cost. In this paper, we propose a parallel sorting method which provides linear speedup of an optimal serial algorithm for a system with a large number of processors. This algorithm may even provide superlinear speedup for a practical system. The algorithm takes advantage of an interconnection network properties and its protocol.