• 마이크로전자및패키징학회지
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• 제21권4호
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• pp.33-39
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• 2014

To establish the reliability of a packaging structures, adhesion testing of key interfaces is a critical task. Due to the material mismatch, the interface may be prone to delamination failure due to conditions during the manufacturing of the product or just from the day-to-day use. To assess the reliability of the interface adhesion strength testing can be performed during the design phase of the product. One test method of interest is the four-point bending (4PB) adhesion strength test method. This test method has been implemented in a variety of situations to evaluate the adhesion strength of interfaces in bimaterial structures to the interfaces within thin film multilayer stacks. This article presents a review of the 4PB adhesion strength testing method and key implementations of the technique in regards to semiconductor packaging.

• 월간포장계
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• 통권166호
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• pp.108-121
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• 2007

• 월간포장계
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• 통권253호
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• pp.42-44
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• 2014

• 한국포장학회지
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• 제16권1호
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• pp.19-25
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• 2010

It is becoming increasingly important to utilize alternative raw materials for plastic industries other than petrochemical-based plastics. Cellulose derivatives were the bases of the original synthetic plastics. Cellulose and its derivatives, especially the widely used cellulose acetate (CA), constitute one of the main classes of raw materials for production on artificial fibers, films, plastics etc. CA is one of the well known polymers produced from naturally available plant substance. Many researches have focused on the isolation of cellulose from the plant cells to use them as cellulose derivatives and composite materials. Chemical and mechanical treatments provide changes on the molecular structures influencing the fundamental properties of these naturally abundant polymer. The aim of this review article is to review biodegradation, synthesis, formation, and utilization of cellulose esters, especially di-acetate, used in packaging related researches.

• 마이크로전자및패키징학회지
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• 제20권4호
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• pp.53-58
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• 2013

An innovative packaging solution, Flip Chip with Copper (Cu) Column bond on lead (BOL) Enhanced Process (fcCuBE$^{(R)}$) delivers a cost effective, high performance packaging solution over typical bond on capture pad (BOC) technology. These advantages include improved routing efficiency on the substrate top layer thus allowing conversion functionality; furthermore, package cost is lowered by means of reduced substrate layer count and removal of solder on pad (SOP). On the other hand, as electronic packaging technology develops to meet the miniaturization trend from consumer demand, reliability testing will become an important issue in advanced technology area. In particular, electromigration (EM) of flip chip bumps is an increasing reliability concern in the manufacturing of integrated circuit (IC) components and electronic systems. This paper presents the results on EM characteristics on BOL and BOC structures under electrical current stressing in order to investigate the comparison between two different typed structures. EM data was collected for over 7000 hours under accelerated conditions (temperatures: $125^{\circ}C$, $135^{\circ}C$, and $150^{\circ}C$ and stress current: 300 mA, 400 mA, and 500 mA). All samples have been tested without any failures, however, we attempted to find morphologies induced by EM effects through cross-sectional analysis and investigated the interfacial reaction characteristics between BOL and BOC structures under current stressing. EM damage was observed at the solder joint of BOC structure but the BOL structure did not show any damage from the effects of EM. The EM data indicates that the fcCuBE$^{(R)}$ BOL Cu column bump provides a significantly better EM reliability.

• 한국복합재료학회:학술대회논문집
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• 한국복합재료학회 2000년도 춘계학술발표대회 논문집
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• pp.175-183
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• 2000

The internal residual stresses within the multilayered structure with shan interface induced by the difference in thermal expansion coefficient between the materials of adjacent layers often provide the source of failure such as delamination of interfaces and etc. Recent development of the multilayered structure with functionally graded interface would be the solution to prevent this kind of failure. However a systematic thermo-mechanical analysis is needed fur the customized structural design of multilayered structure. In this study, theoretical model for the thermo-mechanical analysis is developed for multilayered structures of the Al-$SiC_p$ functionally graded composite for electronic packaging. The evolution of curvature and internal stresses in response to temperature variations is presented for the different combinations of geometry. The resultant analytical solutions are used for the optimal design of the multilayered structures with functionally graded interface as well as with sharp interface.

• 비파괴검사학회지
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• 제30권3호
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• pp.236-243
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• 2010

Fiber Bragg grating(FBG) sensor arrays can be used to monitor the mechanical behavior of the large composite structures such as wind turbine rotor blades and aircrafts. However, brittle FBG sensors, especially multiplexed FBG sensors are easily damaged when they are installed in the flexible structures. As a protection of brittle FBG sensors, epoxy packaged FBG sensors have been presented in this paper. Finite element analysis and experiments were performed to evaluate the effects of adhesives, packaging materials and the bonding layer thickness on the strain transmission. Two types of epoxy were used for packaging FBG sensors and the sensor probes were attached with various bonding layer thickness. It was observed that thin bonding layer with high elastic modulus ratio of the adhesive to packaging provided good strain transmission. However, the strain transmission was significantly decreased when elastic modulus of the adhesive was much lower than the packaged FBG sensor probe's one.

• 반도체디스플레이기술학회지
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• 제20권4호
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• pp.167-170
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• 2021

Integrated passive device (IPD) technology has emerged with the need for 5G. In order to integrate and miniaturize capacitors inside IPD, various studies are actively performed using high-k materials and trench structures. In this paper, an EM(Electromagnetic) simulation study was performed by applying an oxide dielectric to the capacitors having a various trench type structures. Commercially available materials HfO₂, Al₂O₃, and Ta₂O₅ are applied to non, circle, trefoil, and quatrefoil type trench structures to confirm changes in each material or structure. As a result, the bigger the capacitor area and the higher dielectric constant of the oxide dielectric, the insertion loss tended to decrease.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.45-46
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• 2006

An ultrawide bandpass filter with sharp rejection and wider stopband is designed and implemented using multilayer ceramic configuration. The proposed filter is composed of a broadside coupled structure and a ring type filter with an embedded stripline stub. The measured results show that the fractional bandwidth and upper stopband of the proposed filter are 106 % and better than -30 dB, respectively. The insertion loss is less than 1 dB, and group delay is less than 0.3 ns in the passband. In addition, ring and broadside coupled gap structures are characterized and compared to the proposed structure.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 International Symposium
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• pp.165-172
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• 2003

Wafer-level packaging technology has become established with increase of demands for miniaturizing and realizing lightweight electronic devices evolution. This packaging technology enables the smallest footprint of packaged chip. Various structures and processes has been proposed and manufactured currently, and products taking advantages of wafer-level package come onto the market. The package enables mounting semiconductor chip on print circuit board as is a case with conventional die-level CSP's with BGA solder bumps. Bumping technology is also advancing in both lead-free solder alternative and wafer-level processing such as stencil printing using solder paste. It is known lead-free solder bump formation by stencil printing process tend to form voids in the re-flowed bump. From the result of FEM analysis, it has been found that the strain in solder joints with voids are not always larger than those of without voids. In this paper, characteristics of wafer-level package and effect of void in solder bump on its reliability will be discussed.