• 한국소프트웨어감정평가학회 논문지
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• 제17권1호
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• pp.11-16
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• 2021

정보통신의 발달로 인하여 소프트웨어의 중요성이 증대되고 있으며, 이에 따른 소프트웨어 저작권 분쟁도 증가하는 추세에 있다. 본 논문은 제출된 프로그램들의 소스와 관련하여 프로그램 수행에 필요한 파일들을 감정범위로 하였다. 분석 대상인 대용량 파일 전송 솔루션 프로그램은 데이터에 대한 전자서명 및 암호화를 통하여 기밀성, 무결성, 사용자 인증, 부인방지 기능 등의 부가 기능을 제공하고 있다. 본 논문에서는 프로그램 A, 프로그램 B, 프로그램 C 3개에 대하여 분석을 수행한다. 프로그램 유사율을 산출하기 위하여 다음과 같은 내용을 분석한다. 패키지의 구조, 패키지 이름, 각 패키지 내 소스파일 이름, 소스파일 내 변수명, 함수명, 함수구현 소스코드, 제품의 환경변수 정보에 대하여 유사 여부를 분석하고 프로그램의 전체 유사율을 산출한다. 패키지 구조 및 패키지 이름이 일치되는 정도를 확인하기 위해, 폴더 구조를 비교하여 유사도 판단을 하였다. 또한 패키지 구조 및 패키지 이름이 어느 정도 일치하는지와 각 패키지 내 소스 파일(클래스) 이름이 어느 정도 일치하는지에 대한 분석을 하였다.

• 마이크로전자및패키징학회지
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• 제25권4호
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• pp.59-66
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• 2018

본 논문에서는 수치해석을 사용하여 반도체용 패키지에 적용된 인쇄회로기판 (PCB(printed circuit board)) 구조를 다층 구조의 소재 특성을 모델링한 것과 단일 구조라고 가정한 모델링을 적용하여 warpage를 해석함으로써 단일 구조 PCB 모델링의 유용성을 분석하였다. 해석에는 3층과 4층 회로층을 갖는 PCB가 사용되었다. 또한 단일 구조 PCB의 재료 특성값을 얻기 위해 실제 제품을 대상으로 측정을 수행하였다. 해석 결과에 의하면 PCB를 다층 구조로 모델링한 경우에 비해 단일 구조로 모델링한 경우에 warpage가 증가하여 PCB 구조의 모델링에 따른 warpage 분석결과가 분명한 유의차가 있었다. 또한, PCB의 회로층이 증가하면 PCB의 기계적 특성인 탄성계수와 관성모멘트가 증가하여 패키지의 warpage가 감소하였다.

• 수산해양교육연구
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• 제28권2호
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• pp.456-464
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• 2016

NCS development for construction of marine terminal structure was carried out through following procedures such as analysis on characteristics, analysis on duty, development of the first draft for standards, validation of industry sites, duty competency standards through expert committee, and utilizing package. The results were as follows. Firstly, duty competency was classified as levels from 3 to 7. Educational training institutions were followed by 22 universities, 21 colleges, 16 graduate schools, and 10 high schools. Secondly, developed standards were consisted of duty and competency unit. The name of duty was construction of marine terminal structure and competency units were consisted of 9 items as survey on economic effect, evaluation of conditions on construction environment, plan for construction of structure, construction of transfer, mooring, and power equipment, and construction, startup test, and maintenance of terminal structure. 33 competency unit elements below 9 competency units were developed. Thirdly, utilizing package was developed into 3 areas of life-long career path, training criteria, and guidelines for exam according to national competency standards for in order to develop development of labor's career and perform personal management such as hiring and promotion in industry sites.

• Journal of Welding and Joining
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• 제17권6호
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• pp.78-83
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• 1999

Solder joint is the weakest part which connects in mechanically and electronically between package body and PCB(Printed Circuit Board). Recently, the reliability of solder joint become the most critical issue in surface mounted technology. The solder joint interconnection between plastic package and PCB is susceptible to shear stress during thermal storage due to the mismatch in coefficient of thermal expansion between plastic package and PCB. A general computational approach to determine the effect of solder joint shape on the fatigue life presented. The thermal fatigue life was estimated from the engelmaier equation which was obtained from the temperature cycling loading($-65^{\circ}C$ to $150^{\circ}C$). As result of the simulation, TSOP structure has the shortest thermal fatigue life and the same structure Copper lead has 2.5 times as much fatigue life as Alloy 42 lead. In BGA structure, fatigue life time extended 80 times when underfill material exists.

• 전자공학회논문지A
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• 제32A권12호
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• pp.149-158
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• 1995

This paper describes the development of a software tool LCD FRAME that may guide the analyzing process for the electrical characteristics and the design procedure for constructing the thin film transistor liquid crystal display(TFT/LCD) packages. LCD FRAME can analyze its electrical characteristics from the TFT/LCD system package configuration, and provide the design variables to meet the user's requirements. These analysis and design procedure can be done in real time according to the model at simplified package level of TFT/LCD. LCD_FRAME is an object-oriented expert system which considers package elements as objects. With this LCD_FRAME software tool, we analyzed the I-V characteristics of a-Si TFT and its signal distortion which has maximum 1.58 $\mu$s delay along the panel scan line of the package containing 480 ${\times}$ 240 pixels. We designed the package structure of maximum 6.35 $\mu$s signal delays and 3360 ${\times}$ 780 pixels, and as a result we showed that the proper structure of 20 $\mu$m scan line width, 60$\mu$m panel TFT gate width and 8 $\mu$m gate length. This LCD_FRAME software tool provides results of the analysis and the design in the form of input files of the SPICE program, text data files, and graphic charts.

• 대한기계학회논문집
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• 제6권4호
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• pp.384-389
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• 1982

It is necessary that machine tool structures should be designed so that they will cause a minimum chance of machining chatter. In order to do this, a computer program package is developed utilizing Finite Element Method, modal flexibility and energy balance method. Validity of the program package is verified through computer simulation analysis and impulse test of a simplified machine tool structure.

• 한국광학회지
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• 제24권6호
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• pp.342-346
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• 2013

고출력 LED 패키지의 방열 특성 향상을 위하여, 다이 접합부에 실리콘 접착제와 금속 패턴의 병렬 접합 구조를 적용하여 열 유동 해석을 수행하였다. 그 결과, LED 칩에서 발생한 열은 주로 금속 패턴 구조물을 통해 기판으로 효과적으로 전달되고 있으나, 패턴 구조물의 크기에 따라 효율의 차이가 있음을 확인하였고, 그 효과를 정량화하기 위해 정규화 길이를 도입하여 칩과 금속 패턴 구조물의 면적에 따른 열 저항을 비교하였다. 정규화 길이가 길어지면 금속 패턴 구조물에 의한 열 우회 경로가 칩에 고르게 분포하여 열 저항이 감소하였으며, 그 값은 단순 병렬 열 저항 이론 값보다 다소 큰 수치로 수렴하지만, 충분한 열 저항 개선 효과를 얻을 수 있었다.

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2004년도 추계학술발표대회 개요집
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• pp.58-60
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• 2004

In the field of welding the behavior of a welded structure under consideration may be predicted via heat transfer and residual stress analysis. In order to facilitate the industrial applications of welding, numerical modeling of heat transfer and residual stress in weldment has been carried out applying Finite Element Method (FEM) and the analysis with the external load including this residual stress due to welding has been done. The present work includes the specialized finite element codes for the calculation of nonlinear heat transfer details and residual stress redistributed along with the external load in the welded structures. A basic interface, which allows models, built in commercial preprocessing package access to the data necessary to build standard input decks for these specialized FEM codes, which are not supported by commercial package. The results from the FEM codes are imported back into commercial package for visualization. In addition the residual stress values are exported to commercial package (such as ANSYS, PATRAN etc.) for further analysis with the external loads, which make the FEM codes fully applicable to the industrial purpose.

• 한국포장학회지
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• 제12권1호
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• pp.45-53
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• 2006

Thermal insulation is used in a variety of applications to protect temperature sensitive products from thermal damage. Several factors affect the performance of insulation packages. Among these factors, the thermal resistance of the insulating wall is the most important factor to determine the performance of the insulating package. In many cases, insulating wall consists of multi-layered structure and the heat transfer through this structure is a very complex process. In this study, an one-dimensional mathematical model, which includes all of the heat transfer principles covering conduction, convection and radiation in multi-layered structure, were developed. Based on this model, several heat transfer phenomena occurred in the air space between the layer of the insulating wall were investigated. From the simulation results, it was observed that the heat transfer through the air space between the layer were dominated by conduction and radiation and the low emissivity of the surface of each solid layer of the wall can dramatically increase the thermal resistance of the wall. For practical use, an equation was derived for the calculation of the thermal resistance of a multi-layered wall.

• 한국공작기계학회논문집
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• 제17권3호
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• pp.14-19
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• 2008

In the semiconductor IC(Integrated Circuit) package, the top surface of silicon chip is directly attached to the area of the leadframe with a double-sided adhesive layer, in which the base layer have the upper adhesive layer and the lower adhesive layer. The IC package structure has been known to encounter a thermo-mechanical failure mode such as delamination. This failure mode is due to the residual stress on the adhesive surface of silicon chip and leadframe in the curing-cooling process. The induced thermal stress in the curing process has an influence on the cooling residual stress on the silicon chip and leadframe. In this paper, for the minimization of the chip surface damage, the adhesive topologies on the silicon chip are studied through the finite element analysis(FEA).