• Title/Summary/Keyword: package structure analysis

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Appraisal Method for Similarity of Large File Transfer Software (대용량 파일 전송 소프트웨어의 동일성 감정 방법)

  • Chun, Byung-Tae
    • Journal of Software Assessment and Valuation
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    • v.17 no.1
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    • pp.11-16
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    • 2021
  • The importance of software is increasing due to the development of information and communication, and software copyright disputes are also increasing. In this paper, the source of the submitted programs and the files necessary for the execution of the program were taken as the scope of analysis. The large-capacity file transfer solution program to be analyzed provides additional functions such as confidentiality, integrity, user authentication, and non-repudiation functions through digital signature and encryption of data.In this paper, we analyze the program A, program B, and the program C. In order to calculate the program similarity rate, the following contents are analyzed. Analyze the similarity of the package structure, package name, source file name in each package, variable name in source file, function name, function implementation source code, and product environment variable information. It also calculates the overall similarity rate of the program. In order to check the degree of agreement between the package structure and the package name, the similarity was determined by comparing the folder structure. It also analyzes the extent to which the package structure and package name match and the extent to which the source file (class) name within each package matches.

Numerical Study on Package Warpage as Structure Modeling Method of Materials for a PCB of Semiconductor Package (반도체 패키지용 PCB의 구조 모델링 방법에 따른 패키지의 warpage 수치적 연구)

  • Cho, Seunghyun;Ceon, Hyunchan
    • Journal of the Microelectronics and Packaging Society
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    • v.25 no.4
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    • pp.59-66
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    • 2018
  • In this paper, we analyzed the usefulness of single-structured printed circuit board (PCB) modeling by using numerical analysis to model the PCB structure applied to a package for semiconductor purposes and applying modeling assuming a single structure. PCBs with circuit layer of 3rd and 4th were used for analysis. In addition, measurements were made on actual products to obtain material characteristics of a single structure PCB. The analysis results showed that if the PCB was modeled in a single structure compared to a multi-layered structure, the warpage analysis results resulting from modeling the PCB structure would increase and there would be a significant difference. In addition, as the circuit layer of the PCB increased, the mechanical properties of the PCB, the elastic coefficient and inertia moment of the PCB increased, decreasing the package's warpage.

A Study on Duty Competency and Utilizing Package Development for Construction of Marine Terminal Structure (해양터미널구조물설치분야 직무능력 및 활용패키지 개발에 대한 연구)

  • PARK, Jong-Un;KANG, Beodeul;BAEK, In-Hum
    • Journal of Fisheries and Marine Sciences Education
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    • v.28 no.2
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    • pp.456-464
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    • 2016
  • NCS development for construction of marine terminal structure was carried out through following procedures such as analysis on characteristics, analysis on duty, development of the first draft for standards, validation of industry sites, duty competency standards through expert committee, and utilizing package. The results were as follows. Firstly, duty competency was classified as levels from 3 to 7. Educational training institutions were followed by 22 universities, 21 colleges, 16 graduate schools, and 10 high schools. Secondly, developed standards were consisted of duty and competency unit. The name of duty was construction of marine terminal structure and competency units were consisted of 9 items as survey on economic effect, evaluation of conditions on construction environment, plan for construction of structure, construction of transfer, mooring, and power equipment, and construction, startup test, and maintenance of terminal structure. 33 competency unit elements below 9 competency units were developed. Thirdly, utilizing package was developed into 3 areas of life-long career path, training criteria, and guidelines for exam according to national competency standards for in order to develop development of labor's career and perform personal management such as hiring and promotion in industry sites.

A Study on the Thermal Fatigue of Solder Joint by Package Types (패키지 유형에 따른 솔더접합부의 열피로에 관한 연구)

  • 김경섭;신영의
    • Journal of Welding and Joining
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    • v.17 no.6
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    • pp.78-83
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    • 1999
  • Solder joint is the weakest part which connects in mechanically and electronically between package body and PCB(Printed Circuit Board). Recently, the reliability of solder joint become the most critical issue in surface mounted technology. The solder joint interconnection between plastic package and PCB is susceptible to shear stress during thermal storage due to the mismatch in coefficient of thermal expansion between plastic package and PCB. A general computational approach to determine the effect of solder joint shape on the fatigue life presented. The thermal fatigue life was estimated from the engelmaier equation which was obtained from the temperature cycling loading($-65^{\circ}C$ to $150^{\circ}C$). As result of the simulation, TSOP structure has the shortest thermal fatigue life and the same structure Copper lead has 2.5 times as much fatigue life as Alloy 42 lead. In BGA structure, fatigue life time extended 80 times when underfill material exists.

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Development of a Tool for the Electrical Analysis and Design of TFT/LCD System Package (TFT/LCD 시스템 패키지 전기적 특성 분석 및 설계도구의 구현)

  • Yim, Ho-Nam;Jee, Yong
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.32A no.12
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    • pp.149-158
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    • 1995
  • This paper describes the development of a software tool LCD FRAME that may guide the analyzing process for the electrical characteristics and the design procedure for constructing the thin film transistor liquid crystal display(TFT/LCD) packages. LCD FRAME can analyze its electrical characteristics from the TFT/LCD system package configuration, and provide the design variables to meet the user's requirements. These analysis and design procedure can be done in real time according to the model at simplified package level of TFT/LCD. LCD_FRAME is an object-oriented expert system which considers package elements as objects. With this LCD_FRAME software tool, we analyzed the I-V characteristics of a-Si TFT and its signal distortion which has maximum 1.58 $\mu$s delay along the panel scan line of the package containing 480 ${\times}$ 240 pixels. We designed the package structure of maximum 6.35 $\mu$s signal delays and 3360 ${\times}$ 780 pixels, and as a result we showed that the proper structure of 20 $\mu$m scan line width, 60$\mu$m panel TFT gate width and 8 $\mu$m gate length. This LCD_FRAME software tool provides results of the analysis and the design in the form of input files of the SPICE program, text data files, and graphic charts.

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Dynamic Analysis and Optimization of a Machine Tool Structure (工作機械構造 의 動的 解析 및 最適化)

  • 한규환;이장무
    • Transactions of the Korean Society of Mechanical Engineers
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    • v.6 no.4
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    • pp.384-389
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    • 1982
  • It is necessary that machine tool structures should be designed so that they will cause a minimum chance of machining chatter. In order to do this, a computer program package is developed utilizing Finite Element Method, modal flexibility and energy balance method. Validity of the program package is verified through computer simulation analysis and impulse test of a simplified machine tool structure.

Heat Conduction Analysis of Metal Hybrid Die Adhesive Structure for High Power LED Package (고출력 LED 패키지의 열 전달 개선을 위한 금속-실리콘 병렬 접합 구조의 특성 분석)

  • Yim, Hae-Dong;Choi, Bong-Man;Lee, Dong-Jin;Lee, Seung-Gol;Park, Se-Geun;O, Beom-Hoan
    • Korean Journal of Optics and Photonics
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    • v.24 no.6
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    • pp.342-346
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    • 2013
  • We present the thermal analysis result of die bonding for a high power LED package using a metal hybrid silicone adhesive structure. The simulation structure consists of an LED chip, silicone die adhesive, package substrate, silicone-phosphor encapsulation, Al PCB and a heat-sink. As a result, we demonstrate that the heat generated from the chip is easily dissipated through the metal structure. The thermal resistance of the metal hybrid structure was 1.662 K/W. And the thermal resistance of the total package was 5.91 K/W. This result is comparable to the thermal resistance of a eutectic bonded LED package.

STUDY ON THE EFFECT OF RESIDUAL STRESS ON THE EXTERNALLY LOADED WELDED STRUCTURE

  • Rajesh S.R.;Bang Han Sur;Joo Sung Min;Kim In Sik
    • Proceedings of the KWS Conference
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    • v.43
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    • pp.58-60
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    • 2004
  • In the field of welding the behavior of a welded structure under consideration may be predicted via heat transfer and residual stress analysis. In order to facilitate the industrial applications of welding, numerical modeling of heat transfer and residual stress in weldment has been carried out applying Finite Element Method (FEM) and the analysis with the external load including this residual stress due to welding has been done. The present work includes the specialized finite element codes for the calculation of nonlinear heat transfer details and residual stress redistributed along with the external load in the welded structures. A basic interface, which allows models, built in commercial preprocessing package access to the data necessary to build standard input decks for these specialized FEM codes, which are not supported by commercial package. The results from the FEM codes are imported back into commercial package for visualization. In addition the residual stress values are exported to commercial package (such as ANSYS, PATRAN etc.) for further analysis with the external loads, which make the FEM codes fully applicable to the industrial purpose.

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The Analysis of Heat Transfer through the Multi-layered Wall of the Insulating Package

  • Choi, Seung-Jin
    • KOREAN JOURNAL OF PACKAGING SCIENCE & TECHNOLOGY
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    • v.12 no.1
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    • pp.45-53
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    • 2006
  • Thermal insulation is used in a variety of applications to protect temperature sensitive products from thermal damage. Several factors affect the performance of insulation packages. Among these factors, the thermal resistance of the insulating wall is the most important factor to determine the performance of the insulating package. In many cases, insulating wall consists of multi-layered structure and the heat transfer through this structure is a very complex process. In this study, an one-dimensional mathematical model, which includes all of the heat transfer principles covering conduction, convection and radiation in multi-layered structure, were developed. Based on this model, several heat transfer phenomena occurred in the air space between the layer of the insulating wall were investigated. From the simulation results, it was observed that the heat transfer through the air space between the layer were dominated by conduction and radiation and the low emissivity of the surface of each solid layer of the wall can dramatically increase the thermal resistance of the wall. For practical use, an equation was derived for the calculation of the thermal resistance of a multi-layered wall.

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The Stress Analysis of Semiconductor Package (반도체 패키지의 응력 해석)

  • Lee, Jeong-Ick
    • Transactions of the Korean Society of Machine Tool Engineers
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    • v.17 no.3
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    • pp.14-19
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    • 2008
  • In the semiconductor IC(Integrated Circuit) package, the top surface of silicon chip is directly attached to the area of the leadframe with a double-sided adhesive layer, in which the base layer have the upper adhesive layer and the lower adhesive layer. The IC package structure has been known to encounter a thermo-mechanical failure mode such as delamination. This failure mode is due to the residual stress on the adhesive surface of silicon chip and leadframe in the curing-cooling process. The induced thermal stress in the curing process has an influence on the cooling residual stress on the silicon chip and leadframe. In this paper, for the minimization of the chip surface damage, the adhesive topologies on the silicon chip are studied through the finite element analysis(FEA).