• Transactions on Electrical and Electronic Materials
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• 제5권4호
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• pp.138-142
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• 2004

This paper presents the improved bum-in method for the reliability of SRAM in Multi Chip Package (MCP). Semiconductor reliability is commonly improved through the bum-in process. Reliability problem is more significant in MCP that includes over two chips in a package, because the failure of one chip (SRAM) has a large influence on the yield and quality of the other chips - Flash Memory, DRAM, etc. Therefore, the quality of SRAM must be guaranteed. To improve the quality of SRAM, we applied the improved wafer level bum-in process using multi cells selection method in addition to the previously used methods. That method is effective in detecting special failure. Finally, with the composition of some kind of methods, we could achieve the high quality of SRAM in Multi Chip Package.

• 대한기계학회논문집A
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• 제28권11호
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• pp.1646-1655
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• 2004

A description of the basic principles of moire interferometry leads to the design of a eight-mirror four-beam interferometer for obtaining fringe patterns representing contour-maps of in-Plane displacements. The technique is implemented by the optical system using an environmental chamber for submicro-displacement mesurement. In order to estimate the reliability and applicabili쇼 of the system developed, the measurement of coefficient of thermal expansion (CTE) for a aluminium block is performed. Consequently, the system is applied to the measurement of thermal deformation of a WB-PBGA package assembly. Temperature dependent analyses of global and local deformations are presented to study the effect of the mismatch of CTE between materials composed of the package assemblies. Bending displacements of the packages and average strains of solder balls are documented. Thermal induced displacements calculated by FEM agree quantitatively with experimental results.

• 마이크로전자및패키징학회지
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• 제27권1호
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• pp.55-65
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• 2020

반도체 패키지에서 언더필의 사용은 패키지의 응력 완화 및 습기 방지에 중요할 뿐만 아니라, 충격, 진동 시에 패키지의 신뢰성을 향상시키는 중요한 소재이다. 그러나 최근 패키지의 크기가 커지고, 매우 얇아짐에 따라서 언더필의 사용이 오히려 패키지의 신뢰성을 저하하는 현상이 발견되고 있다. 이러한 이슈를 해결하기 위하여 본 연구에서는 언더필을 대신 할 소재로서 solid epoxy를 이용한 패키지를 개발하여 신뢰성을 향상시키고자 하였다. 개발된 solid epoxy를 스마트 폰의 AP 패키지에 적용하여 열사이클링 신뢰성 시험과 수치해석을 통하여 패키지의 신뢰성을 평가하였다. 신뢰성 향상을 위한 최적의 solid epoxy 소재 및 공정 조건을 찾기 위하여 solid epoxy 의 사용 개수, PCB 패드 타입 및 solid epoxy의 물성 등, 3 개의 인자가 패키지의 신뢰성에 미치는 영향을 고찰하였다. Solid epoxy를 AP 패키지에 적용한 결과 solid epoxy가 없는 경우 보다, solid epoxy를 적용한 경우가 신뢰성이 향상되었다. 또한 solid epoxy를 패키지의 외곽 4곳에 적용한 경우 보다는 6 곳에 적용한 경우가 더 신뢰성이 좋음을 알 수 있었다. 이는 solid epoxy가 패키지의 열팽창에 따른 응력을 완화 시키는 역할을 하여 패키지의 신뢰성이 향상되었음을 의미한다. 또한 PCB 패드 타입에 대한 신뢰성을 평가한 결과 NSMD (non-solder mask defined) 패드를 사용할 경우가 SMD (solder mask defined) 패드 보다 신뢰성이 더 향상됨을 알 수 있었다. NSMD 패드의 경우 솔더와 패드가 접합하는 면적이 더 크기 때문에 구조적으로 안정하여 신뢰성 측면에서 더 유리하기 때문이다. 또한 열팽창계수가 다른 solid epoxy를 적용하여 신뢰성 평가를 한 결과, 열팽창계수가 낮은 solid epoxy를 사용한 경우가 신뢰성이 더 향상됨을 알 수 있었다.

• 대한전자공학회논문지SD
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• 제43권11호
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• pp.8-13
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• 2006

최근 RF용 탄성표면파 필터는 HTCC 패키지를 이용한 칩스케일 패키지 공법으로 제작되고 있다. 본 연구에서는 HTCC 패키지를 이용하는 대신에 BT 레진 계열의 PCB 기판을 이용하여 $1.4{\times}1.1$과 $2.0{\times}1.4mm$ 규격을 가지는 새로운 SAW RF 필터를 개발하였다. 본 기술을 적용하여 기존대비 약 40% 이상의 재료비 절감효과를 얻을 수 있다. 다층 PCB 기판과 $LiTaO_3$ 탄성표면파 기간간의 플립 본딩 조건을 최적화하였고, 적절한 PCB 재료선정을 통하여 PCB 기판 및 에폭시 라미네이팅 필름간의 열팽창계수 차이로 인해 발생하는 응력을 최소화시켰다. 이렇게 개발된 탄성표면파 필터는 기존의 제품에 비해 신뢰성 및 전기적 특성면에서 향상된 특성을 보였다.

• 마이크로전자및패키징학회지
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• 제21권3호
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• pp.7-17
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• 2014

Power electronics modules are semiconductor components that are widely used in airplanes, trains, automobiles, and energy generation and conversion facilities. In particular, insulated gate bipolar transistors(IGBT) have been widely utilized in high power and fast switching applications for power management including power supplies, uninterruptible power systems, and AC/DC converters. In these days, IGBT are the predominant power semiconductors for high current applications in electrical and hybrid vehicles application. In these application environments, the physical conditions are often severe with strong electric currents, high voltage, high temperature, high humidity, and vibrations. Therefore, IGBT module packages involves a number of challenges for the design engineer in terms of reliability. Thermal and thermal-mechanical management are critical for power electronics modules. The failure mechanisms that limit the number of power cycles are caused by the coefficient of thermal expansion mismatch between the materials used in the IGBT modules. All interfaces in the module could be locations for potential failures. Therefore, a proper thermal design where the temperature does not exceed an allowable limit of the devices has been a key factor in developing IGBT modules. In this paper, we discussed the effects of various package materials on heat dissipation and thermal management, as well as recent technology of the new package materials.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2009년도 춘계학술발표대회
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• pp.3.2-3.2
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• 2009

Development of printed electronics, which is occasionally referred to as 'flexible' or 'polymer' electronics, has attracted considerable world wide attention in recent years. Printed (or flexible) electronics is currently expected to represent a new form of electronics and open up wide ranging applications in displays, electron devices for medical use, sensors, and other areas. This presentation aims to provide a strategy for scalable and viable paths to accomplish flexible, printable, large area circuits displaying high performance. Novel approaches evolving from system on package (SoP) to system on flex (SoF) technology will allow the integration of heterogeneous materials platforms into a system which is needed to enhance the functionality of the system. The talk also includes speculations about areas on which future advances in printed electronics could have a substantial impact along with a brief introduction of the Korea Printed Electronics Association (KoPEA).

• Journal of Welding and Joining
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• 제24권2호
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• pp.64-70
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• 2006

The 3-dimensional (3D) chip stacking technology is a leading technology to realize a high density and high performance system in package (SiP). There are several kinds of methods for chip stacking, but the stacking and interconnection through Cu filled through-hole via is considered to be one of the most advanced stacking technologies. Therefore, we studied the optimum process of through-hole via formation and Cu filling process for Si wafer stacking. Through-hole via was formed with DRIE (Deep Reactive ion Etching) and Cu filling was realized with the electroplating method. The optimized conditions for the via formation were RE coil power of 200 W, etch/passivation cycle time of 6.5 : 6 s and SF6 : C4F8 gas flow rate of 260 : 100 sccm. The reverse pulsed current of 1.5 A/dm2 was the most favorable condition for the Cu electroplating in the via. The Cu filled Si wafer was chemically and mechanically polished (CMP) for the following flip chip bumping technology.

• 한국결정성장학회지
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• 제10권6호
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• pp.407-411
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• 2000

전자 package용 저온봉착 유리를 실험적으로 합성하고 이 유리의 결정화 거동을 비등온 조건하에서 열분석기(DTA)를 이용하여 조사하였다. 이 유리의 조성을 미량의 CaO, $SiO_2$$A1_2$$O_3$ 및 $P_2$$O_5$ 등이 함유된 PbO-ZnO-$B_2$$O_3$-$TiO_2$유리로부터 결정하였다. 연 티탄산염($PbTiO_3$)생성에 해당되는 결정화 발열이 관찰되었다. 이 $PbTiO_3$의 결정화는 삼차원과정으로 진행되었고 유리기지(glass matrix)로부터 생성되는 이 결정의 평균 활성화에너지는 223$\pm$3 kJ/mo1 이었다.

• 한국정밀공학회지
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• 제31권10호
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• pp.857-863
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• 2014

In this work, we introduce various bonding technologies for 3D package and suggest Insert-Bump bonding (ISB) process newly to stack multi-layer chips successively. Microstructure of Insert-Bump bonding (ISB) specimens is investigated with respect to bonding parameters. Through experiments, we study on find optimal bonding conditions such as bonding temperature and bonding pressure and also evaluate in the case of fluxing and no-fluxing condition. Although no-fluxing bonding process is applied to ISB bonding process, good bonding interface at $270^{\circ}C$ is formed due to the effect of oxide layer breakage.

• 조명전기설비학회논문지
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• 제29권4호
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• pp.1-10
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• 2015

The light emitting diodes(LED) package of new structure is proposed to promote the reliability and lifespan by maximize heat dissipation occurred on the chip. We designed and fabricated the LED packages mixing the advantages of chip on board(COB) based on conventional metal printed circuit board(PCB) and the merits of Si sub-mount using base as a substrate. The proposed LED package samples were selected for the superior efficiency of the material through the sealant properties, chip characteristics, and phosphor properties evaluations. Reliability test was conducted the thermal shock test and flux rate according to the usage time at room temperature, high-temperature operation, high-temperature operation, high-temperature storage, low-temperature storage, high-temperature and high-humidity storage. Reliability test result, the average flux rate was maintained at 97.04% for each items. Thus, the Si sub-mount based LED package is expected to be applicable to high power down-light type LED light sources.