• Title/Summary/Keyword: p-type silicon wafer

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A Study on Feasibility of the Phosphoric Paste Doping for Solar Cell using Newly Atmospheric Pressure Plasma Source (새로운 대기압 플라즈마 소스를 이용한 결정질 실리콘 태양전지 인(P) 페이스트 도핑에 관한 연구)

  • Cho, I-Hyun;Yun, Myoung-Soo;Jo, Tae-Hoon;Rho, Junh-Young;Jeon, BuII;Kim, In-Tae;Choi, Eun-Ha;Cho, Guang-Sup;Kwon, Gi-Chung
    • New & Renewable Energy
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    • v.9 no.2
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    • pp.23-29
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    • 2013
  • Furnace and laser is currently the most important doping process. However furnace is typically difficult appling for selective emitters. Laser requires an expensive equipment and induces a structural damage due to high temperature using laser. This study has developed a new atmospheric pressure plasma source and research atmospheric pressure plasma doping. Atmospheric pressure plasma source injected Ar gas is applied a low frequency (a few 10 kHz) and discharged the plasma. We used P type silicon wafers of solar cell. We set the doping parameter that plasma treatment time was 6s and 30s, and the current of making the plasma is 70 mA and 120 mA. As result of experiment, prolonged plasma process time and highly plasma current occur deeper doping depth and improve sheet resistance. We investigated doping profile of phosphorus paste by SIMS (Secondary Ion Mass Spectroscopy) and obtained the sheet resistance using generally formula. Additionally, grasped the wafer surface image with SEM (Scanning Electron Microscopy) to investigate surface damage of doped wafer. Therefore we confirm the possibility making the selective emitter of solar cell applied atmospheric pressure plasma doping with phosphorus paste.

A Study on Micro Gas Sensor Utilizing $WO_3$Thin Film Fabricated by Sputtering Method (스파터링법에 의해 제작된 $WO_3$박막을 이용한 마이크로 가스센서에 관한 연구)

  • 이영환;최석민;노일호;이주헌;이재홍;김창교;박효덕
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2000.07a
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    • pp.471-474
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    • 2000
  • A flat type microgas sensor was fabricated on the p-type silicon wafer with low stress S $i_3$ $N_4$, whose thickness is 2${\mu}{\textrm}{m}$ using MEMS technology and its characteristics were investigated. W $O_3$thin film as a sensing material for detection of N $O_2$gas was deposited using a tungsten target by sputtering method, followed by thermal oxidation at several temperatures (40$0^{\circ}C$~$600^{\circ}C$) for one hour. N $O_2$gas sensitivities were investigated for the W $O_3$thin films with different annealing temperatures. The highest sensitivity when operating at 20$0^{\circ}C$ was obtained for the samples annealed at $600^{\circ}C$. As the results of XRD analysis, the annealed samples had polycrystalline phase mixed with triclinic and orthorhombic structures. The sample exhibit higher sensitivity when the system has less triclinic structure. The sensitivities, $R_{gas}$ $R_{air}$ operating at 20$0^{\circ}C$ to 5 ppm N $O_2$of the sample annealed at $600^{\circ}C$ were approximately 90. 90.

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Heterojunction Solar Cell with Carrier Selective Contact Using MoOx Deposited by Atomic Layer Deposition (원자층 증착법으로 증착된 MoOx를 적용한 전하 선택 접합의 이종 접합 태양전지)

  • Jeong, Min Ji;Jo, Young Joon;Lee, Sun Hwa;Lee, Joon Shin;Im, Kyung Jin;Seo, Jeong Ho;Chang, Hyo Sik
    • Korean Journal of Materials Research
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    • v.29 no.5
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    • pp.322-327
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    • 2019
  • Hole carrier selective MoOx film is obtained by atomic layer deposition(ALD) using molybdenum hexacarbonyl[$Mo(CO)_6$] as precursor and ozone($O_3$) oxidant. The growth rate is about 0.036 nm/cycle at 200 g/Nm of ozone concentration and the thickness of interfacial oxide is about 2 nm. The measured band gap and work function of the MoOx film grown by ALD are 3.25 eV and 8 eV, respectively. X-ray photoelectron spectroscopy(XPS) result shows that the $Mo^{6+}$ state is dominant in the MoOx thin film. In the case of ALD-MoOx grown on Si wafer, the ozone concentration does not affect the passivation performance in the as-deposited state. But, the implied open-circuit voltage increases from $576^{\circ}C$ to $620^{\circ}C$ at 250 g/Nm after post-deposition annealing at $350^{\circ}C$ in a forming gas ambient. Instead of using a p-type amorphous silicon layer, high work function MoOx films as hole selective contact are applied for heterojunction silicon solar cells and the best efficiency yet recorded (21 %) is obtained.

A study on point defects induced with neutron irradiation in silicon wafer (중성자 조사에 의해 생성된 점결함 연구)

  • 김진현;이운섭;류근걸;김봉구;이병철;박상준
    • Proceedings of the KAIS Fall Conference
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    • 2002.05a
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    • pp.151-154
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    • 2002
  • 반도체 소자의 기판 재료로 사용되고 있는 실리콘 웨이퍼는 그 정밀도가 매우 중요하다. 본 연구에서는 균일한 Dopant 농도 분포를 얻을 수 있는 중성자 변환 Doping을 이용하여 실리콘에 인(P)을 Doping하는 연구를 수행하였다. 중성자 변환 Doping, 즉 NTD(Neutron Transmutation Doping)란 원자번호 30인 실리콘 동위원소에 중성자가 조사되면 원자번호 31인 실리콘으로 변환되고, 2.6시간의 반감기를 갖고 decay 되면서 인(P)으로 변하게 되어 실리콘 웨이퍼에 n-type 전도를 갖게 하는 것을 말한다. 본 연구에서는 하나로 원자로를 이용하여 고저항(1000-2000Ωcm) FZ 실리콘 웨이퍼 에 두 개의 조사공에서 중성자 조사하여 저항의 변화를 관찰하였고, 중성자 조사시 발생하는 점결함을 분석하여 점결함이 저항 변화에 미치는 영향을 알아보았다. 중성자 조사 전 이론적 계산에 의해 HTS조사공은 5Ωcm, 20.1Ωcm 이고 IP3조사공은 5Ωcm, 26.5Ωcm, 32.5Ωcm 이었고, 중성자 조사 후 SRP로 측정한 결과 실제 저항값은 HTS-1 2.10Ωcm, HTS-2 7.21Ωcm 이었고, IP-1은 1.79Ωcm, IP-2는 6.83Ωcm, 마지막으로 IP-3는 9.23Ωcm 이었다. DLTS 측정 결과 IP조사공에서 새로운 피의 결을 발견할 수 있었다.

Effect of Saw-Damage Etching Conditions on Flexural Strength in Si Wafers for Silicon Solar Cells (태양전지용 실리콘 기판의 절삭손상 식각 조건에 의한 곡강도 변화)

  • Kang, Byung-Jun;Park, Sung-Eun;Lee, Seung-Hun;Kim, Hyun-Ho;Shin, Bong-Gul;Kwon, Soon-Woo;Byeon, Jai-Won;Yoon, Se-Wang;Kim, Dong-Hwan
    • Korean Journal of Materials Research
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    • v.20 no.11
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    • pp.617-622
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    • 2010
  • We have studied methods to save Si source during the fabrication process of crystalline Si solar cells. One way is to use a thin silicon wafer substrate. As the thickness of the wafers is reduced, mechanical fractures of the substrate increase with the mechanical handling of the thin wafers. It is expected that the mechanical fractures lead to a dropping of yield in the solar cell process. In this study, the mechanical properties of 220-micrometer-solar grade Cz p-type monocrystalline Si wafers were investigated by varying saw-damage etching conditions in order to improve the flexural strength of ultra-thin monocrystalline Si solar cells. Potassium hydroxide (KOH) solution and tetramethyl ammonium hydroxide (TMAH) solution were used as etching solutions. Etching processes were operated with a varying of the ratio of KOH and TMAH solutions in different temperature conditions. After saw-damage etching, wafers were cleaned with a modified RCA cleaning method for ten minutes. Each sample was divided into 42 pieces using an automatic dicing saw machine. The surface morphologies were investigated by scanning electron microscopy and 3D optical microscopy. The thickness distribution was measured by micrometer. The strength distribution was measured with a 4-point-bending tester. As a result, TMAH solution at $90^{\circ}C$ showed the best performance for flexural strength.

Fabrication of Microwire Arrays for Enhanced Light Trapping Efficiency Using Deep Reactive Ion Etching

  • Hwang, In-Chan;Seo, Gwan-Yong
    • Proceedings of the Korean Vacuum Society Conference
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    • 2014.02a
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    • pp.454-454
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    • 2014
  • Silicon microwire array is one of the promising platforms as a means for developing highly efficient solar cells thanks to the enhanced light trapping efficiency. Among the various fabrication methods of microstructures, deep reactive ion etching (DRIE) process has been extensively used in fabrication of high aspect ratio microwire arrays. In this presentation, we show precisely controlled Si microwire arrays by tuning the DRIE process conditions. A periodic microdisk arrays were patterned on 4-inch Si wafer (p-type, $1{\sim}10{\Omega}cm$) using photolithography. After developing the pattern, 150-nm-thick Al was deposited and lifted-off to leave Al microdisk arrays on the starting Si wafer. Periodic Al microdisk arrays (diameter of $2{\mu}m$ and periodic distance of $2{\mu}m$) were used as an etch mask. A DRIE process (Tegal 200) is used for anisotropic deep silicon etching at room temperature. During the process, $SF_6$ and $C_4F_8$ gases were used for the etching and surface passivation, respectively. The length and shape of microwire arrays were controlled by etching time and $SF_6/C_4F_8$ ratio. By adjusting $SF_6/C_4F_8$ gas ratio, the shape of Si microwire can be controlled, resulting in the formation of tapered or vertical microwires. After DRIE process, the residual polymer and etching damage on the surface of the microwires were removed using piranha solution ($H_2SO_4:H_2O_2=4:1$) followed by thermal oxidation ($900^{\circ}C$, 40 min). The oxide layer formed through the thermal oxidation was etched by diluted hydrofluoric acid (1 wt% HF). The surface morphology of a Si microwire arrays was characterized by field-emission scanning electron microscopy (FE-SEM, Hitachi S-4800). Optical reflection measurements were performed over 300~1100 nm wavelengths using a UV-Vis/NIR spectrophotometer (Cary 5000, Agilent) in which a 60 mm integrating sphere (Labsphere) is equipped to account for total light (diffuse and specular) reflected from the samples. The total reflection by the microwire arrays sample was reduced from 20 % to 10 % of the incident light over the visible region when the length of the microwire was increased from $10{\mu}m$ to $30{\mu}m$.

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A study on property of crystalline silicon solar cell for variable annealing temperature of SOD (SOD 온도 가변을 이용한 결정질 태양전지 특성 연구)

  • Song, Kyuwan;Jang, Juyeon;Yi, Junsin
    • 한국신재생에너지학회:학술대회논문집
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    • 2011.05a
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    • pp.124.1-124.1
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    • 2011
  • 결정질 태양전지에서 도핑(Doping)은 반도체(Semiconductor)의 PN 접합(Junction)을 형성하는 중요한 역할을 한다. 도핑은 반도체에 불순물(Dopant)을 주입하는 공정으로 고온에서 진행되며 온도는 중요한 변수(Parameter)로 작용한다. 본 연구에서는 여러 가지 도핑 방법 중 SOD(Spin-On Dopant)를 이용하여 온도에 따른 도핑 결과와 특성을 분석 하였다. P-type 웨이퍼(Wafer)에 SOD를 이용하여 불순물을 증착 후 Hot-plate에서 15분간 Baking 하였다. Baking된 웨이퍼는 노(Furnace)에 넣고 $860^{\circ}C{\sim}880^{\circ}C$까지 $10^{\circ}C$씩 가변하였다. 각각의 조건에 대해 Lifetime과 Sheet Resistance을 측정하였고, 그 결과 $880^{\circ}C$에서의 Lifetime이 $23.58{\mu}s$$860^{\circ}C$에 비해 235.8% 증가하여 가장 우수 하였으며, Sheet Resistance 또한 $68{\Omega}$/sq로 $860^{\circ}C$에서 가장 우수하게 측정되었다. SOD의 속도 가변에 따른 특성 변화를 보기 위해 온도는 $880^{\circ}C$에 고정한 후 속도를 3000rpm~4500rpm까지 500rpm간격으로 1시간동안 실험한 결과 rpm 속도에 따른 lifetime 변화는 거의 없었으며, Sheet Resistance는 3000rpm에서 $63{\Omega}$/sq로 가장 우수 하였다. 본 연구를 통해 온도와 Spin rpm에 따른 특성을 확인한 결과 온도가 높을 때 Sheet Resistance가 가장 안정화 되며, lifetime이 더욱 우수한 것을 확인할 수 있었다.

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Study of Thermal Stability of Ni Silicide using Ni-V Alloy

  • Zhong, Zhun;Oh, Soon-Young;Lee, Won-Jae;Zhang, Ying-Ying;Jung, Soon-Yen;Li, Shi-Guang;Lee, Ga-Won;Wang, Jin-Suk;Lee, Hi-Deok;Kim, Yeong-Cheol
    • Transactions on Electrical and Electronic Materials
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    • v.9 no.2
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    • pp.47-51
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    • 2008
  • In this paper, thermal stability of Nickel silicide formed on p-type silicon wafer using Ni-V alloy film was studied. As compared with pure Ni, Ni-V shows better thermal stability. The addition of Vanadium suppresses the phase transition of NiSi to $NiSi_2$ effectively. Ni-V single structure shows the best thermal stability compared with the other Ni-silicide using TiN and Co/TiN capping layers. To enhance the thermal stability up to $650^{\circ}C$ and find out the optimal thickness of Ni silicide, different thickness of Ni-V was also investigated in this work.

Microfabrication of Submicron-size Hole on the Silicon Substrate using ICP etching

  • Lee, J.W.;Kim, J.W.;Jung, M.Y.;Kim, D.W.;Park, S.S.
    • Proceedings of the Korean Vacuum Society Conference
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    • 1999.07a
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    • pp.79-79
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    • 1999
  • The varous techniques for fabrication of si or metal tip as a field emission electron source have been reported due to great potential capabilities of flat panel display application. In this report, 240nm thermal oxide was initially grown at the p-type (100) (5-25 ohm-cm) 4 inch Si wafer and 310nm Si3N4 thin layer was deposited using low pressure chemical vapor deposition technique(LPCVD). The 2 micron size dot array was photolithographically patterned. The KOH anisotropic etching of the silicon substrate was utilized to provide V-groove formation. After formation of the V-groove shape, dry oxidation at 100$0^{\circ}C$ for 600 minutes was followed. In this procedure, the orientation dependent oxide growth was performed to have a etch-mask for dry etching. The thicknesses of the grown oxides on the (111) surface and on the (100) etch stop surface were found to be ~330nm and ~90nm, respectively. The reactive ion etching by 100 watt, 9 mtorr, 40 sccm Cl2 feed gas using inductively coupled plasma (ICP) system was performed in order to etch ~90nm SiO layer on the bottom of the etch stop and to etch the Si layer on the bottom. The 300 watt RF power was connected to the substrate in order to supply ~(-500)eV. The negative ion energy would enhance the directional anisotropic etching of the Cl2 RIE. After etching, remaining thickness of the oxide on the (111) was measured to be ~130nm by scanning electron microscopy.

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Study on the Characteristics of ALD HfO2 Thin Film by using the High Pressure H2 Annealing (고압의 HfO2 가스 열처리에 따른 원자층 증착 H2 박막의 특성 연구)

  • Ahn, Seung-Joon;Park, Chul-Geun;Ahn, Seong-Joon
    • Journal of the Korean Magnetics Society
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    • v.15 no.5
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    • pp.287-291
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    • 2005
  • We have investigated and tried to improve the characteristics of the thin $HfO_2$ layer deposited by ALD for fabricating a MOSFET device where the $HfO_2$ film worked as the gate dielectric. The substrate of MOSFET device is p-type (100) silicon wafer over which the $HfO_2$ dielectric layer with thickness of $5\~6\;nm$ has been deposited. Then the $HfO_2$ film was annealed with $1\~20\;atm\;H_2$ gas and subsequently aluminum electrodes was made so that the active area was $5{\times}10^{-5}\;cm^2$. We have found out that the drain current and transconductance increased by $5\~10\%$ when the $H_2$ gas pressure was 20 atm, which significantly contributed to the reliable operation of the high-density MOSFET devices.