• 대한전자공학회논문지
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• 제23권3호
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• pp.370-375
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• 1986

In this paper, modeling of the conduction mechanism of ion implanted p-type polycrystalline silicon is studied. From this modeling, the resistivity of p-type polycrystalline and its dependence on dopant concentration are calculated. The proposed modeling whose grain size is about 1450 \ulcorneris shwon to agree well with the experimental result.

• 한국태양에너지학회 논문집
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• 제38권1호
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• pp.37-44
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• 2018

Solar panels are modules made up of many cells, like the N-type monosilicon, P-type monosilicon, P-type multisilicon, amorphous thin-film silicon, and CIGS solar cells. An efficient photovoltaic (PV) power is important to use to determine what kind of cell types are used because residential solar systems receive attention. In this study, we used 3-type solar panels - such as N-type monosilicon, P-type monosilicon, and CIGS solar cells - to investigate what kind of solar panel on a house or building performs the best. PV systems were composed of 3-type solar panels on the roof with each ~1.8 kW nominal power. N-type monosilicon solar panel resulted in the best power generation when monitored. Capacity Utilization Factor (CUF) and Performance Ratio (PR) of the N-type Si solar panel were 14.6% and 75% respectively. In comparison, N-type monosilicon and CIGS solar panels showed higher performance in power generation than P-type monosilicon solar power with increasing solar irradiance.

• 전기의세계
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• 제22권5호
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• pp.5-11
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• 1973

A new method of forming silicon p$^{+}$-n-n$^{+}$ junctions has been attempted by using the VDH-Implanter (Vacuum Discharge and Heating). Each of p$^{+}$-n and n-n$^{+}$ junctions was formed on both sides of an n-type silicon substrate by means of predeposition of each dopant and their bombarding due to rarefied air ions together with the preheating of the substrate in the implanter. The recifying principle of the p$^{+}$-n-n$^{+}$ junctions is thought to be based on the theory of double injection. The I-V characteristic of the diode has shown that it has a fairly high forward current density with the desirable rise due to vary low voltage though the reverse voltage is a little low on account of the low resistivity of the silicon substrate.n substrate.

• 한국세라믹학회지
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• 제39권6호
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• pp.594-597
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• 2002

플라즈마 화학기상증착(PECVD)법을 이용하여 p-type Si(100) 웨이퍼에 Silicon Oxynitride(SiON) 후막을 SiH$_4$ , $N_2$O, $N_2$ 가스를 혼합하여 증착하였다. Prism coupler측정을 통해 SiON 후막의 굴절률 1.4620~1.5312을 얻었으며, rf power가 180 W에서 5.92$\mu$m/h의 증착률을 나타내었다. 증착변수에 따른 화학적 조성의 영향은 X-ray Photoelectron Spectroscopy(XPS) 을 통하여 관찰하였다. 또한, SiON 후막 증착후에 $1.5\mu$m 부근의 흡수띠를 제거하기 위해 105$0^{\circ}C$의 $N_2$ 분위기에서 2시간 동안 열처리를 행하였다.

• 한국결정성장학회:학술대회논문집
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• 한국결정성장학회 1996년도 The 9th KACG Technical Annual Meeting and the 3rd Korea-Japan EMGS (Electronic Materials Growth Symposium)
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• pp.494-496
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• 1996

The purpose of this study is to investigate the effect of process conditions on pore distribution in porous silicon layer prepared by electrochemical reaction. Porous silicon layers formed on p-type silicon wafer show the network structure of fine porse whose diameters are less than 100${\AA}$. In n-type porous silicon, selective growth was found on the pore surface by wet etching process after PR patterning. And numerical method showed high current density on the pore tip. With this result we confirmed that pore formation has two steps. First step is the initial attack on the surface and second step is the directional growth on the pore tip.

• Current Photovoltaic Research
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• 제7권1호
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• pp.15-20
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• 2019

Most high-efficiency n-type silicon solar cells are based on the high quality surface passivation and ohmic contact between the emitter and the metal. Currently, various metalization methods such as screen printing using metal paste and physical vapor deposition are being used in forming electrodes of n-type silicon solar cell. In this paper, we analyzed the degradation factors induced by the front electrode formation process using e-beam evaporation of double passivation structure of p-type emitter and $Al_2O_3/SiN_x$ for high efficiency solar cell using n-type bulk silicon. In order to confirm the cause of the degradation, the passivation characteristics of each electrode region were determined through a quasi-steady-state photo-conductance (QSSPC).

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2010년도 춘계학술대회 초록집
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• pp.76.1-76.1
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• 2010

Furnace를 이용한 $POCl_3$ 확산 공정은 실리콘 태양전지 제작과정에서 일반적으로 이용되는 에미터 층 형성 공정이다. 하지만, 확산 공정을 통해 P-N Junction을 형성할 경우 전면과 후면의 contact현상이 발생하게 되고 이를 제거하기 위해 Edge isolation 공정을 거치게 된다. 최근에는 레이저로 V 모양의 홈을 형성하는 방법이 이용되고 있다. 본 연구에서는 p-type 실리콘 웨이퍼 기판에 insulating barrier를 형성하여 edge isolation 공정을 없앤 Non-edge isolation공정을 제시한다. Non p-type 실리콘 웨이퍼에 insulating barrier를 형성한다. Insulating barrier가 형성된 BOE용액과 KOH에서의 견딤성 실험을 진행 하였다. 이후, p-type 단결정 실리콘 태양전지의 확산 공정을 진행하여 Non edge isolation 공정을 진행한 경우와 laser를 이용한 edge isolation 공정을 진행한 태양전지를 제작하여 특성을 비교하였다.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2005년도 춘계학술대회
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• pp.168-171
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• 2005

Thickness optimization of heavily doped p-type seeding layer was studied to improve performance of thin film silicon solar cell. We used liquid phase epitaxy (LPE) to grow active layer of $25{\MU}m$ thickness on p+ seeding layer. The cells with p+ seeding layer of $10{\mu}m\;to\;50{\mu}m$ thickness were fabricated. The highest efficiency of a cell is $12.95\%$, with Voc=633mV, $Jsc=26.5mA/cm^2,\;FF=77.15\%$. The $P^+$ seeding layer of the cell is $20{\mu}m$, thick. As thicker seeding layer than $20{\mu}m$, the performance of the cell was degraded. The results demonstrate that the part of the recombination current is due to the heavily doped seeding layer. Thickness of heavily doped p-type seeding layer was optimized to $20{\mu}m$. The performance of solar cell is expected to improve with the incorporation of light trapping as texturing and AR coating.

• 한국위성정보통신학회논문지
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• 제8권4호
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• pp.124-129
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• 2013

PPS 구조가 삽입된 N형 실리콘 제어 정류기 소자를 마이크로 칩의 고전압 I/O 응용을 위해 연구하였다. 종래의 NSCR_PPS_Std 표준소자는 매우 낮은 스냅백 홀딩 전압을 갖는 전형적인 SCR 특성을 가지고 있어 정상적인 동작 동안 래치업 문제가 나타나는 것으로 보고되고 있다. 그러나 본 연구에서 제안하는 CPS 및 부분적으로 형성된 P-Well(PPW) 구조를 갖는 변형된 NSCR_PPS_CPS_PPW 소자는 높은 래치업 면역과 트리거링 전압의 조절이 용이한 안정한 ESD 보호 성능을 나타내어 고전압 동작용 마이크로 칩의 정전기보호 소자로 적용 가능함을 확인하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.418-418
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• 2008

The electrochemical etching of silicon in HF-based solutions is known to form various types of porous structures. Porous structures are generally classified into three categories according to pore sizes: micropore (below 2 nm in size), mesopore (2 ~ 50 nm), and macropore (above 50 nm). Recently, the formation of macropores has attracted increasing interest because of their promising characteristics for an wide scope of applications such as microelectromechanical systems (MEMS), chemical sensors, biotechnology, photonic crystals, and photovoltaic application. One of the promising applications of macropores is in the field of MEMS. Anisotropic etching is essential step for fabrication of MEMS. Conventional wet etching has advantages such as low processing cost and high throughput, but it is unsuitable to fabricate high-aspect-ratio structures with vertical sidewalls due to its inherent etching characteristics along certain crystal orientations. Reactive ion dry etching is another technique of anisotropic etching. This has excellent ability to fabricate high-aspect-ratio structures with vertical sidewalls and high accuracy. However, its high processing cost is one of the bottlenecks for widely successful commercialization of MEMS. In contrast, by using electrochemical etching method together with pre-patterning by lithographic step, regular macropore arrays with very high-aspect-ratio up to 250 can be obtained. The formed macropores have very smooth surface and side, unlike deep reactive ion etching where surfaces are damaged and wavy. Especially, to make vertical microwire or nanowire arrays (aspect ratio = over 1:100) on silicon wafer with top-down photolithography, it is very difficult to fabricate them with conventional dry etching. The electrochemical etching is the most proper candidate to do it. The pillar structures are demonstrated for n-type silicon and the formation mechanism is well explained, while such a experimental results are few for p-type silicon. In this report, In order to understand the roles played by the kinds of etching solution and mask patterns in the formation of microwire arrays, we have undertaken a systematic study of the solvent effects in mixtures of HF, dimethyl sulfoxide (DMSO), iso-propanol, and mixtures of HF with water on the structure formation on monocrystalline p-type silicon with a resistivity with 10 ~ 20 $\Omega{\cdot}cm$. The different morphological results are presented according to mask patterns and etching solutions.