• 한국산학기술학회논문지
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• 제19권3호
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• pp.576-583
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• 2018

탄화규소는 실리콘과 비교시 큰 에너지 밴드 갭을 갖고, 불순물 도핑에 의해 p형 및 n형 전도의 제어가 용이해서 고온용 전자부품 소재로 활용이 가능한 재료이다. 특히 ${\beta}$-SiC 분말로부터 제조한 다공질 n형 SiC 세라믹스의 경우, $800{\sim}1000^{\circ}C$에서 높은 열전 변환 효율을 나타내었다. SiC 열전 변환 반도체를 응용하기 위해서는 변환 성능지수도 중요하지만 $800^{\circ}C$ 이상에서 사용할 수 있는 고온용 금속전극 또한 필수적이다. 일반적으로 세라믹스는 대부분의 보편적인 용접용 금속과는 우수한 젖음을 갖지 못 하지만, 활성 첨가물을 고용시킨 합금의 경우, 계면 화학종들의 변화가 가능해서 젖음과 결합의 정도를 증진시킬 수 있다. 액체가 고체 표면을 적시면 액체-고체간 접합면의 에너지는 고체의 표면에너지 보다 작아지고 그 결과 액체가 고체 표면에서 넓게 퍼지면서 모세 틈새로 침투할 수 있는 구동력을 갖게 된다. 따라서 본 연구에서는 비교적 낮은 융점을 갖는 Ag를 이용해서 다공질 SiC 반도체 / Ag 및 Ag 합금 / SiC 및 알루미나 기판간의 접합에 대해 연구하였고, Ag-20Ti-20Cu 필러 메탈의 경우 SiC 반도체의 고온용 전극으로 적용 가능할 것으로 나타났다.

• 대한전자공학회논문지
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• 제26권6호
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• pp.30-37
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• 1989

Silane($SiH_4$), methane($CH_4$), diborane(B_2H_6)그리고 phosphine($PH_3$)을 이용하여 rf글로방전분해법으로 PIN형 a-SiC:H/a-Si:H 이종접합 태양전지를 제작하였다. $SnO_2/ITO$층 형성치 태양전지의 효율은 ITO 투명전극만의 경우보다 1.5% 향상되었다. 제작조건은 P층의 경우 $CH_4/SiH_4$의 비를 5로 하고 두께는 $100{\AA}$이었다. I층은 P층위에 증착하였으나 진성이 아니고 N형에 가깝다. 이 I층을 진성으로 바꾸기 위해서 0.3ppm의 $B_2H_6$를 $SiH_4$에 혼합하여 5000${\AA}$증착했다. 또한 N층은 $PH_4/SiH_4$의 비를 $10^{-2}$로 하여 $400{\AA}$ 증착시켰다. 그 결과 입사강도가 15mW/$cm^2$일 때 개방전압 $V_{oc}=O'$단락전류밀도 $J_{sc=14.6mA/cm^2}$, 충진율 FF=58.2%, 그리고 효율 ${eta}=8.0%$를 나타내었다. 빛의 반사에 의한 손실을 감소시키기 위하여 $MgF_2$를 유리기판위에 도포하였다. 이에 의한 효율은 0.5% 향상되어 전체적인 효율은 8.5%였다.

• Current Photovoltaic Research
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• 제2권4호
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• pp.147-151
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• 2014

A boron doping process using a boron tri-bromide ($BBr_3$) as a boron source was applied to form a $p^+$ emitter layer on an n-type mono-crystalline CZ substrate. Nitrogen ($N_2$) gas as an additive of the diffusion process was varied in order to study the variations in sheet resistance and the uniformity of doped layer. The flow rate of $N_2$ gas flow was changed in the range 3 slm~10 slm. The sheet resistance uniformity however was found to be variable with the variation of the $N_2$ flow rate. The optimal flow rate for $N_2$ gas was found to be 4 slm, resulting in a sheet resistance value of $50{\Omega}/sq$ and having a uniformity of less than 10%. The process temperature was also varied in order to study its influence on the sheet resistance and minority carrier lifetimes. A higher lifetime value of $1727.72{\mu}s$ was achieved for the emitter having $51.74{\Omega}/sq$ sheet resistances. The thickness of the boron rich layer (BRL) was found to increase with the increase in the process temperature and a decrease in the sheet resistance was observed with the increase in the process temperature. Furthermore, a passivated emitter solar cell (PESC) type solar cell structure comprised of a boron doped emitter and phosphorus doped back surface field (BSF) having Ni/Cu contacts yielding 15.32% efficiency is fabricated.

• 한국재료학회지
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• 제20권11호
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• pp.617-622
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• 2010

We have studied methods to save Si source during the fabrication process of crystalline Si solar cells. One way is to use a thin silicon wafer substrate. As the thickness of the wafers is reduced, mechanical fractures of the substrate increase with the mechanical handling of the thin wafers. It is expected that the mechanical fractures lead to a dropping of yield in the solar cell process. In this study, the mechanical properties of 220-micrometer-solar grade Cz p-type monocrystalline Si wafers were investigated by varying saw-damage etching conditions in order to improve the flexural strength of ultra-thin monocrystalline Si solar cells. Potassium hydroxide (KOH) solution and tetramethyl ammonium hydroxide (TMAH) solution were used as etching solutions. Etching processes were operated with a varying of the ratio of KOH and TMAH solutions in different temperature conditions. After saw-damage etching, wafers were cleaned with a modified RCA cleaning method for ten minutes. Each sample was divided into 42 pieces using an automatic dicing saw machine. The surface morphologies were investigated by scanning electron microscopy and 3D optical microscopy. The thickness distribution was measured by micrometer. The strength distribution was measured with a 4-point-bending tester. As a result, TMAH solution at $90^{\circ}C$ showed the best performance for flexural strength.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.454-454
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• 2014

Silicon microwire array is one of the promising platforms as a means for developing highly efficient solar cells thanks to the enhanced light trapping efficiency. Among the various fabrication methods of microstructures, deep reactive ion etching (DRIE) process has been extensively used in fabrication of high aspect ratio microwire arrays. In this presentation, we show precisely controlled Si microwire arrays by tuning the DRIE process conditions. A periodic microdisk arrays were patterned on 4-inch Si wafer (p-type, $1{\sim}10{\Omega}cm$) using photolithography. After developing the pattern, 150-nm-thick Al was deposited and lifted-off to leave Al microdisk arrays on the starting Si wafer. Periodic Al microdisk arrays (diameter of $2{\mu}m$ and periodic distance of $2{\mu}m$) were used as an etch mask. A DRIE process (Tegal 200) is used for anisotropic deep silicon etching at room temperature. During the process, $SF_6$ and $C_4F_8$ gases were used for the etching and surface passivation, respectively. The length and shape of microwire arrays were controlled by etching time and $SF_6/C_4F_8$ ratio. By adjusting $SF_6/C_4F_8$ gas ratio, the shape of Si microwire can be controlled, resulting in the formation of tapered or vertical microwires. After DRIE process, the residual polymer and etching damage on the surface of the microwires were removed using piranha solution ($H_2SO_4:H_2O_2=4:1$) followed by thermal oxidation ($900^{\circ}C$, 40 min). The oxide layer formed through the thermal oxidation was etched by diluted hydrofluoric acid (1 wt% HF). The surface morphology of a Si microwire arrays was characterized by field-emission scanning electron microscopy (FE-SEM, Hitachi S-4800). Optical reflection measurements were performed over 300~1100 nm wavelengths using a UV-Vis/NIR spectrophotometer (Cary 5000, Agilent) in which a 60 mm integrating sphere (Labsphere) is equipped to account for total light (diffuse and specular) reflected from the samples. The total reflection by the microwire arrays sample was reduced from 20 % to 10 % of the incident light over the visible region when the length of the microwire was increased from $10{\mu}m$ to $30{\mu}m$.

• Current Photovoltaic Research
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• 제9권3호
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• pp.75-83
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• 2021

The tunnel oxide passivated contact (TOPCon) structure got more consideration for development of high performance solar cells by the introduction of a tunnel oxide layer between the substrate and poly-Si is best for attaining interface passivation. The quality of passivation of the tunnel oxide layer clearly depends on the bond of SiO in the tunnel oxide layer, which is affected by the subsequent annealing and the tunnel oxide layer was formed in the suboxide region (SiO, Si₂O, Si₂O₃) at the interface with the substrate. In the suboxide region, an oxygen-rich bond is formed as a result of subsequent annealing that also improves the quality of passivation. To control the surface morphology, annealing profile, and acceleration rate, an oxide tunnel junction structure with a passivation characteristic of 700 mV or more (V_oc) on a p-type wafer could achieved. The quality of passivation of samples subjected to RTP annealing at temperatures above 900℃ declined rapidly. To improve the quality of passivation of the tunnel oxide layer, the physical properties and thermal stability of the thin layer must be considered. TOPCon silicon solar cell has a boron diffused front emitter, a tunnel-SiO_x/n⁺-poly-Si/SiN_x:H structure at the rear side, and screen-printed electrodes on both sides. The saturation currents J_o of this structure on polished surface is 1.3 fA/cm² and for textured silicon surfaces is 3.7 fA/cm² before printing the silver contacts. After printing the Ag contacts, the J_o of this structure increases to 50.7 fA/cm² on textured silicon surfaces, which is still manageably less for metal contacts. This structure was applied to TOPCon solar cells, resulting in a median efficiency of 23.91%, and a highest efficiency of 24.58%, independently. The conversion efficiency of interdigitated back-contact solar cells has reached up to 26% by enhancing the optoelectrical properties for both-sides-contacted of the cells.

• 대한전자공학회논문지TE
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• 제39권1호
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• pp.31-36
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• 2002

낮은 에너지의 보론 이온을 선비정질화된 실리콘 기판과 단결정 기판에 이온 주입하여 0.2μm 정도의 접합 깊이를 갖는 박막의 P/sup +/-n 접합을 형성하였다 이온주입에 의한 결정결함의 제거 및 주입된 보론 이온의 활성화를 위해 급속 열처리기를 이용하였으며, BPSC(bore-phosphosilicate glass)를 흐르도록 하기 위해 노 열처리를 도입하였다. 선비정질화 이온주입은 45keV, 3×10/sup 14/cm/sup -2/ Ge 이온을 사용하였으며, p형 불순물로는 BF2 이온을 20keV, 2×10/sup 15/cm /sup -2/로 이온주입 하였다. 급속 열처리와 노 열처리 조건은 각각 1000。C/ 10초와 850。C/4O분이었다. 형성된 접합의 접합깊이는 SIMS와 ASR로 측정하였으며, 4-point probe로 면 저항을 측정하였다. 또한 전기적인 특성은 다이오드에 역방향 전압을 인가하여 측정된 누설전류로 분석하였다. 측정 결과를 살펴보면, 급속 열처리만을 수행하여도 양호한 접합 특성을 나타내나, 급속 열처리와 노 열처리를 함께 고려해야 할 경우에는 노 열처리 후에 급속 열처리를 수행하는 공정이 급속 열처리 후에 노 열처리를 수행하는 경우보다 더 우수한 박막 접합 특성을 나타내었다.

• Journal of Electrical Engineering and Technology
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• 제9권5호
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• pp.1654-1659
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• 2014

Tunneling field-effect transistors (TFETs) are very applicable to low standby-power application by their virtues of low off-current ($I_{off}$) and small subthreshold swing (S). However, low on-current ($I_{on}$) of silicon-based TFETs has been pointed out as a drawback. To improve $I_{on}$ of TFET, a gate-all-around (GAA) TFET based on III-V compound semiconductor with InAs/InGaAs/InP multiple-heterojunction structure is proposed and investigated. Its performances have been evaluated with the gallium (Ga) composition (x) for $In_{1-x}Ga_xAs$ in the channel region. According to the simulation results for $I_{on}$, $I_{off}$, S, and on/off current ratio ($I_{on}/I_{off}$), the device adopting $In_{0.53}Ga_{0.47}As$ channel showed the optimum direct-current (DC) performance, as a result of controlling the Ga fraction. By introducing an n-type InGaAs thin layer near the source end, improved DC characteristics and radio-frequency (RF) performances were obtained due to boosted band-to-band (BTB) tunneling efficiency.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2010년도 춘계학술대회 초록집
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• pp.76.2-76.2
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• 2010

질산 용액을 이용한 처리를 통해서 실리콘 웨이퍼 위에 누설 전류가 thermal oxidation 방법과 비슷한 수준의 얇은 실리콘 산화막을 형성할 수 있다. 이러한 처리 방법은 thermal oxidation에 비해서 낮은 온도에서 공정이 가능하다는 장점을 가진다. 이 때 질산 용액으로 68 wt% $HNO_3$을 쓰는데, 이 용액에만 넣었을 때에는 실리콘 산화막이 어느 정도 두께 이상은 성장하지 않는 단점이 있다. 그렇기 때문에 실리콘 웨이퍼를 68 wt% $HNO_3$에 넣기 전에 seed layer 산화막을 형성 시킨다. 본 연구에서는 p-type 웨이퍼를 phosphorus로 도핑해서 에미터를 형성 시킨 후에 seed layer를 형성 시키고 68 wt% $HNO_3$를 이용해서 에미터 위의 실리콘 산화막을 성장 시켰다. 이 때 보다 더 효과적인 seed layer를 형성 시키는 용액을 찾아서 실험하였다. 40 wt% $HNO_3$, $H_2SO_4-H_2O_2$, HCl-$H_2O_2$ 용액에 웨이퍼를 10분 동안 담그는 것을 통해서 seed layer를 형성하고, 이를 $121^{\circ}C$인 68 wt% $HNO_3$에 넣어서 실리콘 산화막을 성장시켰다. 이렇게 형성된 실리콘 산화막의 특성은 엘립소미터, I-V 측정 장치, QSSPC를 통해서 알아보았다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.65-65
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• 2009

High temperature silicon carbide Schottky diode was fabricated with Au deposited on poly 3C-SiC thin film grown on p-type Si(100) using atmospheric pressure chemical vapor deposition. The charge transport mechanism of the diode was studied in the temperature range of 300 K to 550 K. The forward and reverse bias currents of the diode increase strongly with temperature and diode shows a non-ideal behavior due to the series resistance and the interface states associated with 3C-SiC. The charge transport mechanism is a temperature activated process, in which, the electrons passes over of the low barriers and in turn, diode has a large ideality factor. The charge transport mechanism of the diode was analyzed by a Gaussian distribution of the Schottky barrier heights due to the Schottky barrier inhomogeneities at the metal-semiconductor interface and the mean barrier height and zero-bias standard deviation values for the diode was found to be 1.82 eV and $s_0$=0.233 V, respectively. The interface state density of the diode was determined using conductance-frequency and it was of order of $9.18{\times}10^{10}eV^{-1}cm^{-2}$.