• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.357-357
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• 2012

The doping process of the solar cell has been used by furnace or laser. But these equipment are so expensive as well as those need high maintenance costs and production costs. The atmospheric pressure plasma doping process can enable to the cost reduction. Moreover the atmospheric pressure plasma can do the selective doping, this means is that the atmospheric pressure plasma regulates the junction depth and doping concentration. In this study, we analysis the atmospheric pressure plasma doping compared to the conventional furnace doping. the single crystal silicon wafer doped with dopant forms a P-N junction by using the atmospheric pressure plasma. We use a P type wafer and it is doped by controlling the plasma process time and concentration of dopant and plasma intensity. We measure the wafer's doping concentration and depth by using Secondary Ion Mass Spectrometry (SIMS), and we use the Hall measurement because of investigating the carrier concentration and sheet resistance. We also analysis the composed element of the surface structure by using X-ray photoelectron spectroscopy (XPS), and we confirm the structure of the doped section by using Scanning electron microscope (SEM), we also generally grasp the carrier life time through using microwave detected photoconductive decay (u-PCD). As the result of experiment, we confirm that the electrical character of the atmospheric pressure plasma doping is similar with the electrical character of the conventional furnace doping.

• Korean Journal of Materials Research
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• v.14 no.2
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• pp.90-93
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• 2004

Silicon dioxide thin films were deposited on p-type Si (100) substrates by atomic layer deposition (ALD) method using alternating exposures of $SiH_2$$Cl_2$ and $O_3$ at $300^{\circ}C$. $O_3$ was generated by corona discharge inside the delivery line of $O_2$. The oxide film was deposited mainly from $O_3$ not from $O_2$, because the deposited film was not observed without corona discharge under the same process conditions. The growth rate of the deposited films increased linearly with increasing the exposures of $SiH_2$$Cl_2$ and $O_3$ simultaneously, and was saturated at approximately 0.35 nm/cycle with the reactant exposures over $3.6 ${\times}$ 10^{9}$ /L. At a fixed $SiH_2$$Cl_2$ exposure of $1.2 ${\times}$ 10^{9}$L, growth rate increased with $O_3$ exposure and was saturated at approximately 0.28 nm/cycle with $O_3$ exposures over$ 2.4 ${\times}$ 10^{9}$ L. The composition of the deposited film also varied with the exposure of $O_3$. The [O]/[Si] ratio gradually increased up to 2 with increasing the exposure of $O_3$. Finally, the characteristics of ALD films were compared with those of the silicon oxide films deposited by conventional chemical vapor deposition (CVD) methods. The silicon oxide film prepared by ALD at $300^{\circ}C$ showed better stoichiometry and wet etch rate than those of the silicon oxide films deposited by low-pressure CVD (LPCVD) and atmospheric-pressure CVD (APCVD) at the deposition temperatures ranging from 400 to $800^{\circ}C$.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.4
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• pp.29-33
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• 2003

Material and electrical properties of copper-based ohmic contacts on n-type 4H-SiC were investigated for the effects of the post-annealing and the metal covering conditions. The ohmic contacts were prepared by sequential sputtering of Cu and Si layers on SiC substrate. The post-annealing treatment was performed using RTP (rapid thermal process) in vacuum and reduction ambient. The specific contact resistivity ($p_{c}$), sheet resistance ($R_{s}$), contact resistance ($R_{c}$), transfer length ($L_{T}$), were calculated from resistance (RT) versus contact spacing (d) measurements obtained from TLM (transmission line method) structure. The best result of the specific contact resistivity was obtained for the sample annealed in the reduction ambient as $p_{c}= 1.0 \times 10^{-6}\Omega \textrm{cm}^2$. The material properties of the copper contacts were also examined by using XRD. The results showed that copper silicide was formed on SiC as a result of intermixing Cu and Si layer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.131-131
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• 2008

Silicon carbide (SiC) has attracted significant attention for high frequency, high temperature and high power devices due to its superior properties such as the large band gap, high breakdown electric field, high saturation velocity and high thermal conductivity. We performed Al ion implantation processes on n-type 4H-SiC substrate using a SILVACO ATHENA numerical simulator. The ion implantation model used a Monte-Carlo method. We studied the effect of channeling by Al implantation simulation in both 0 off-axis and 8 off-axis n-type 4H-SiC substrate. We have investigated the Al distribution in 4H-SiC through the variation of the implantation energies and the corresponding ratio of the doses. The implantation energies controlled 40, 60, 80, 100 and 120 keV and the implantation doses varied from $2\times10^{14}$ to $1\times10^{15}cm^{-2}$. In the simulation results, the Al ion distribution was deeper as increasing implantation energy and the doping level increased as increasing implantation doses. After the post-implantation annealing, the electrical properties of Al-implanted p-n junction diode were investigated by SILV ACO ATLAS numerical simulator.

• Proceedings of the KIEE Conference
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• 2003.07c
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• pp.1938-1940
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• 2003

본 연구는 요소 센서 제작을 위한 과정으로서, 전기화학적 방법을 이용한 다공질 실리콘 구조 형성과, PDV(Physical Vapor Deposition) 법에 의한 백금 박막 코팅 및 전기화학적 전도성 고분자 코팅과 urease 고정화 단계를 고찰하고 감도 특성을 제시 하였다. 전극 기질로서 B을 도우핑한 p-type 실리콘웨이퍼를 사용하였고, HF:$C_2H_5OH:H_2O$=1:2:1의 부피비를 갖는 에칭 용액에서 5분간 -7 $mA/cm^2$의 일정 전류를 가하여 폭 2 ${\mu}m$, 깊이 10 ${\mu}m$의 다공질 실리콘(PS) 충을 형성하였다. 그 위에 200 ${\AA}$의 Ti 층을 underlayer로서 증착하고, 2000 ${\AA}$의 Pt를 중착하여 PS/Pt 박막 전극을 제작하고, 전도성 고분자로서 polypyrrole (PPy), 또는 poly(3-mehylthiophene) (P3MT)을 전기화학적으로 코팅한 후, urease(EC 3.5.1.5, type III, Jack Bean, Sigma)를 고정화 하였다. 고정화 시 전해질 수용액의 pH는 7.4로 하여 urease표면이 음전하를 갖도록 하고, 전극에 0.6 V (vs. SCE(Saturated Calomel Electrode))의 일정 전압을 가함으로써 urease가 전도성 고분자 표면에 전기적으로 흡착되도록 하였다. 이상의 방법으로 제작한 요소 센서의 감도는 PPy와 P3MT를 전자 전달 매질로 사용한 경우, 각각 8.44 ${\mu}A/mM{\cdot}cm^2$와 1.55 ${\mu}A/mM{\cdot}cm^2$의 감도를 보였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.8
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• pp.481-485
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• 2015

We investigated the effects of annealing on the electrical and thermal properties of ZTO/4H-SiC heterojunction diodes. A ZTO thin film layer was grown on p-type 4H-SiC substrate by using solution process. The ZTO/SiC heterojunction structures annealed at $500^{\circ}C$ show that $I_{on}/I_{off}$ increases from ${\sim}5.13{\times}10^7$ to ${\sim}1.11{\times}10^9$ owing to the increased electron concentration of ZTO layer as confirmed by capacitance-voltage characteristics. In addition, the electrical characterization of ZTO/SiC heterojunction has been carried out in the temperature range of 300~500 K. When the measurement temperature increased from 300 K to 500 K, the reverse current variation of annealed device is higher than as-grown device, which is related to barrier height in the ZTO/SiC interface. It is shown that annealing process is possible to control the electrical characteristics of ZTO/SiC heterojunction diode.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.22 no.3_1spc
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• pp.504-508
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• 2013

This paper describes in detail the life prediction models and simulations of thermal fatigue under different mold compounds and chip sizes for wafer-level embedded SiP. Three-dimensional finite element models are built to simulate the viscoplastic behaviors for various mold compounds and chip sizes. In particular, the bonding parts between a mold and silicon nitride (Si3N4) are carefully modeled, and the strain distributions are studied. Three different chip sizes are used, and the effects of the mold compounds are observed. Through the numerical studies, it is found that type-C, which has a relatively lower Young's modulus and higher CTE, has a better fatigue life than the other mold compounds. In addition, the $4{\times}4$ chip has a shorter life than the $6{\times}6$ and $8{\times}8$ chips.

• Journal of Magnetics
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• v.2 no.1
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• pp.16-21
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• 1997

Those were investigated, the crystallographic, morphological, and magnetic properties of barium ferrite film (SiO2/Si substrate) prepared by sol-gel dip coating. Appropriate sol was prepared by dissolvin barium and iron nitrate in ethylene glycol at 80$^{\circ}C$. To obtain the films, thermally oxidized p-type silicon substrate with (111) of crystallographic orientation were dipped into the sol, dried at 250$^{\circ}C$ to remove organic material, and heated at 800$^{\circ}C$ for 3 hours in air for the crystallization of barium ferrite. It was found that the particles of barium ferrite formed on the substrate exhibited needle-like shape placing parallel to the substrate and its c-axis is long axis direction. There was tendency that the coercive force in horizontal direction to the substrate was higher than that in vertical direction to it. This tendency was profound in large thickness.

• Proceedings of the Korea Association of Crystal Growth Conference
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• 1997.10a
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• pp.117-121
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• 1997

It is shown theoretically that uniform axial dopant concentration distribution can be made throughout the crystal by continuous Czochralski process. Numerical simulation are performed for the transient two-dimensional convection-diffusion model. A typical value of the growth and system parameters for Czochralski growth of p-type, 4 inches silicon crystal was used in the numerical calculations. Using this model with proper model parameter, the axial segregation in batchwise Czochralski growth can be described. It is studied by comparing with the experimental data. With this model parameter, the uniform axial concentration distribution of dopant is predicted in continuous Czochralski process.

• 한국신재생에너지학회:학술대회논문집
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• 2010.11a
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• pp.58.2-58.2
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• 2010

본 연구에서는 n-type wafer에 비정질 실리콘을 증착한 이종접합 태양전지를 열처리 방법을 이용하여 열처리의 효과를 분석함으로써 이종접합 태양전지에 효율적인 열처리 효과에 대하여 연구하였다. P, N-layer는 PECVD(Plasma-enhanced chemical vapor deposition) I-layer는 HWCVD(Hot wire chemical vapor deposition), ITO는 RF 마그네트론 스퍼터링법으로 동일한 조건에서 제작하였고 rapid thermal process를 이용하여 진공 중에서 $150^{\circ}C$, $200^{\circ}C$, $220^{\circ}C$, $250^{\circ}C$까지 열처리를 하였다. 열처리 전과 후 QSSPC로 minority carrier life time, 자외 가시선 분광분석 장치로 투과 반사도를, Ellipsometer로 흡수 계수 등의 변화를 조사하였다. 열처리 후 Minority carrier life time, Voc 및 광변환 효율이 증가하였다.