• Journal of the Korean Vacuum Society
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• v.1 no.1
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• pp.176-182
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• 1992

t-Stress and junction leakage current characteristics of CVD-tungsten have been investigated. Stressversus continuous annealing temperature plot. shows hysteresis curve where the stress level of the cooling curveis higher than that of the heating curve. It is found that the thermal and intrinsic stress of tungsten film depositedby SiH4 reduction is higher than that by Hz reduction.The tungsten film deposited by SiHl reduction is in the tensile stress state below 700"Cnd the stress ofthe film decreses with increasing annealing temperature. The stress state changes into compressive stress atabout 700"Cnd the compressive stress increases rapidly with increasing temperature.Leakage current of the n+/p diode increases rapidly especially in the range of 400-450$^{\circ}$C with increasingdeposition temperature of the CVD-W by SiH4 reduction, which is due to the Si consumption by W encroachment.On the other hand leakage current of the n+/p diode slightly increases with increasing SiH4/WF6 ratio.h increasing SiH4/WF6 ratio.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.306-316
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• 2016

In this paper, an NMOS-diode eFuse OTP (One-Time Programmable) memory cell is proposed using a parasitic junction diode formed between a PW (P-Well), a body of an isolated NMOS (N-channel MOSFET) transistor with the small channel width, and an n+ diffusion, a source node, in a DNW (Deep N-Well) instead of an NMOS transistor with the big channel width as a program select device. Blowing of the proposed cell is done through the parasitic junction formed in the NMOS transistor in the program mode. Sensing failures of '0' data are removed because of removed contact voltage drop of a diode since a NMOS transistor is used instead of the junction diode in the read mode. In addition, a problem of being blown for a non-blown eFuse from a read current through the corresponding eFuse OTP cell is solved by limiting the read current to less than $100{\mu}A$ since a voltage is transferred to BL by using an NMOS transistor with the small channel width in the read mode.

• Journal of Sensor Science and Technology
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• v.5 no.1
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• pp.57-62
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• 1996

To decrease the leakage current of $p^{+}n$ junction diode with hyperabrupt structure, the $3000{\AA}$ polysilicon was deposited on the top of conventional $p^{+}n$ diode and then annealed for 30 minutes at $900^{\circ}C$ in the $N_{2}$ ambient. It was estimated for both $p^{+}n$ diodes with and without polysilicon layer, and the impurity materials of n diffused layer to observe the influence of the polysilicon layer on leakage current characteristics. The leakage current was reduced to the order of 3 by using polysilicon layer. A large number of dislocation loops, which were believed to be generated by As-implanted diffused layer, were found to be removed by using polysilicon through TEM analysis.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.8
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• pp.38-43
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• 1998

An analytical model for the surface field distribution of the RESURF (reduced surface field)LD(lateral double-diffused) MOS is presented in terms of the doping concentration, the thickness of the n epi layer, the p substrate concentration, and the epi layer length. The reuslts are used to determine the breakdown voltage due to the surface field as a function of the epi layer length. The maximum breakdown voltage of the device is found to be that of the vertical n$^{+}$n$^{[-10]}$ p$^{[-10]}$ junction. Analytical results of the breakdown voltage vs. the epi layer length agree well with the numerical simulation results using MEDICI.I.

• Journal of the Korean Institute of Telematics and Electronics
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• v.10 no.3
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• pp.1-9
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• 1973

Gallium phosphide light emitting diode (LED) has been fabricated first time for pilot lamp and numeric display purposes. Bright red light is obtained in forward bias at very low current of one to five mA. A typical p-n junction is formed by liquid phase epitaxial growth on a n-type gallium physphide substrate. The crystal growth is achieved at about 1300$^{\circ}$K after the equilibrium of the gallium solution followed by tipping operation. The ohmic contact is made by wire bonding by thermal compression technique. The entire process is well fit for laboratory scale to fabricate a few hundred diodes for mainly demonstration purpose. For mass production, a large sum of the capital investment is required. The great merit of gallium phosphide LED is at low current operation, and green light emission is also obtainable by nitrogen doping.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.274-274
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• 2010

최근 들어 나노선을 이용한 pn 접합 소자 연구 결과가 매우 활발하게 보고되고 있다. 그러나, 서로 다른 두 종류의 나노선으로 pn 접합 어레이 구조의 소자를 제작할 때, 나노선을 원하는 위치에 정렬하는 기술상의 어려움이 큰 걸림돌이 된다. 본 연구에서는 p-CNT와 n-$SnO_2$ 나노선을 이용한 pn 접합 어레이 구조를 제작할 수 있는 독창적인 공정기술을 제안한다. 먼저 $SiO_2$가 300 nm 성장된 Si 기판을 선택적으로 패터닝하여 BOE (6:1) 용액으로 $SiO_2$ 층을 80 nm 정도 선택적으로 에칭한 후, 선택적으로 에칭된 표면에 슬라이딩 장비를 이용하여 화학기상증착법(chemical vapor deposition: CVD)으로 성장된 n-$SnO_2$ 나노선을 전이시킨다. 그 다음 thermal tape를 이용하여 CVD 법으로 성장된 랜덤 네트워크 형태의 CNT를 $SnO_2$ 나노선이 전이된 기판 위에 전이 시킨다. 이때 성장된 CNT 필름 중 금속성 나노선을 통한 전하 이동을 감소시키기 위해, 촉매로 사용되는 페리틴의 농도를 낮춰서 전체적인 CNT의 농도를 줄이는 방법을 이용하였다. 따라서, 성장된 CNT 필름은 별도의 후처리 없이 p-형의 반도체성을 보였다. 제작된 pn-소자는 정류비가 ~103 인 정류특성을 보였으며, 254 nm 파장의 UV lamp를 조사하여 광전류가 발생하는 것을 확인하였다. 연구결과는 이종의 나노선 접합에 의한 다이오드 응용과 UV 센서응용 가능성을 보여준다.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.382.1-382.1
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• 2014

Graphene field-effect transistors (GFET) is one of candidates for future high speed electronic devices since graphene has unique electronic properties such as high Fermi velocity (vf=10^6 m/s) and carrier mobility ($15,000cm^2/V{\cdot}s$) [1]. Although the contact property between graphene and metals is a crucial element to design high performance electronic devices, it has not been clearly identified. Therefore, we need to understand characteristics of graphene/metal contact in the GFET. Recently, it is theoretically known that graphene on metal can be doped by presence of interface dipole layer induced by charge transfer [2]. It notes that doping type of graphene under metal is determined by difference of work function between graphene and metal. In this study, we present the GFET fabricated by contact metals having high work function (Pt, Ni) for p-doping and low work function (Ta, Cr) for n-doping. The results show that asymmetric conductance depends on work function of metal because the interfacial dipole is locally formed between metal electrodes and graphene. It induces p-n-p or n-p-n junction in the channel of the GFET when gate bias is applied. In addition, we confirm that charge transfer regions are differently affected by gate electric field along gate length.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.3
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• pp.139-143
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• 2017

N-type crystalline silicon solar cells have high metal impurity tolerance and higher minority carrier lifetime that increases conversion efficiency. However, junction quality between the boron diffused layer and the n-type substrate is more important for increased efficiency. In this paper, the current status and prospects for boron diffused layers in N-type crystalline silicon solar cell applications are described. Boron diffused layer formation methods (thermal diffusion and co-diffusion using $a-SiO_X:B$), boron rich layer (BRL) and boron silicate glass (BSG) reactions, and analysis of the effects to improve junction characteristics are discussed. In-situ oxidation is performed to remove the boron rich layer. The oxidation process after diffusion shows a lower B-O peak than before the Oxidation process was changed into $SiO_2$ phase by FTIR and BRL. The $a-SiO_X:B$ layer is deposited by PECVD using $SiH_4$, $B_2H_6$, $H_2$, $CO_2$ gases in N-type wafer and annealed by thermal tube furnace for performing the P+ layer. MCLT (minority carrier lifetime) is improved by increasing $SiH_4$ and $B_2H_6$. When $a-SiO_X:B$ is removed, the Si-O peak decreases and the B-H peak declines a little, but MCLT is improved by hydrogen passivated inactive boron atoms. In this paper, we focused on the boron emitter for N-type crystalline solar cells.

• Journal of the Korean Institute of Telematics and Electronics
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• v.5 no.3
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• pp.9-24
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• 1968

This report is concerned with the optimum design of hyper-aprupt p-n junctiea silion diode and fabriction of this diode usable for electrical tuning application. Impurity profile in the junction was assumed to clean exponential function. With this assunntion, an optimum criterion for designing standard AM radio tuning capacitor was derived. In the diffusion process, after aluminum and antimony as impurties were deposited in vacuum on a P-type silicon wafer, the diffusion was followed by loading the wafer into the high temperature furnace.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2000.11a
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• pp.17-20
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• 2000

This study is about a retrograde triple well employed in the Cell tr. of next DRAM and flash memory. triple well structure is formed deep n-well under the light p-well using MeV ion implantation. MeV P implanted deep n-well was observed to show greatly improved characteristics of electrical isolation and soft error. Junction leakage current, however, showed a critical behavior as a function of implantation and annealing conditions. {311} defects were observed to be responsible for the leakage current. {311} defects were generated near the R$\sub$p/ (projected range) region and grown upward to the surface during annealing. This is study on the defect behavior in device region as a function of implantation and annealing conditions.