• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.11C
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• pp.1120-1127
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• 2006

[ $GF(2^m)$ ] for elliptic curve cryptosystem. The proposed multiplier uses Gaussian normal basis representation and produces multiplication results at a rate of one per [m/w] clock cycles, where w is the selected we.4 size. We implement the p.oposed design using Xilinx XC2V1000 FPGA device. Our design has significantly less critical path delay compared with previously proposed hard ware implementations.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.7
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• pp.1-8
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• 2008

Low Density Parity Check codes(LDPC) are recently focused on communication systems due to its good performance. The standard of WiBro has also included LDPC codes as a channel coding. The weak point of implementation for LDPC encoder is that conventional binary Matrix Vector Multiplier has many clock cycles which limit throughput. In this paper, we propose semi-parallel architecture by using cyclic shift registers and exclusive-OR without conventional Matrix Vector Multipliers over the standard parity check matrices with Circulant Permutation Matrices(CPM). Furthermore, multi-rate encoder is designed by using proposed architecture. Our encoder with multi-rate for IEEE 802.16e LDPC has lower clock cycles and higher throughput.

• Geomechanics and Engineering
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• v.31 no.5
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• pp.505-518
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• 2022

This study introduces soil resistance multipliers at locations encompassed by the zone of influence of the helix plate to consider the added lateral resistance provided to the helical pile. The zone of influence of a helix plate is a function of its diameter and serves as a boundary condition for the modified soil resistance springs. The concept is based on implementing p-multipliers as a reduction factor for piles in group action. The application of modified p-y springs in the analysis of helical piles allows for better characterization and understanding of the lateral behavior of helical piles, which will help further the development of design methods. To execute the proposed method, a finite difference program, HPCap (Helical Pile Capacity), was developed by the authors using Matlab. The program computes the deflection, shear force, bending moment, and soil resistance of the helical pile and allows the user to freely input the value of the zone of influence and Ω (a coefficient that affects the value of the p-multiplier). Results from ten full-scale lateral load tests on helical piles embedded at depths of 3.0 m with varying shaft diameters, shaft thicknesses, and helix configurations were analyzed to determine the zone of influence and the magnitude of the p-multipliers. The analysis determined that the value of the p-multipliers is influenced by the ratio between the pile embedment length and the shaft diameter (D_p), the effective helix diameter (D_h-D_p), and the zone of influence. Furthermore, the zone of influence is recommended to be 1.75 times the helix diameter (D_h). Using the numerical analysis method presented in this study, the predicted deflections of the various helical pile cases showed good agreement with the observed field test results.

• Journal of IKEEE
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• v.24 no.4
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• pp.961-968
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• 2020

This paper describes a design of high performance modular multiplier that is essentially used for elliptic curve cryptography. Our modular multiplier supports modular multiplications for five field sizes over GF(p), including 192, 224, 256, 384 and 521 bits as defined in NIST FIPS 186-2, and it calculates modular multiplication in two steps with integer multiplication and reduction. The Karatsuba-Ofman multiplication algorithm was used for fast integer multiplication, and the Lazy reduction algorithm was adopted for reduction operation. In addition, the Nikhilam division algorithm was used for the division operation included in the Lazy reduction. The division operation is performed only once for a given modulo value, and it was designed to skip division operation when continuous modular multiplications with the same modulo value are calculated. It was estimated that our modular multiplier can perform 6.4 million modular multiplications per second when operating at a clock frequency of 32 MHz. It occupied 456,400 gate equivalents (GEs), and the estimated clock frequency was 67 MHz when synthesized with a 180-nm CMOS cell library.

• Nonlinear Functional Analysis and Applications
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• v.26 no.1
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• pp.65-70
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• 2021

We characterize the solution set for a second-order cone linear fractional optimization problem (P). We present sequential Lagrange multiplier characterizations of the solution set for the problem (P) in terms of sequential Lagrange multipliers of a known solution of (P).

• Journal of Broadcast Engineering
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• v.21 no.3
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• pp.319-329
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• 2016

Internet Video Coding (IVC) is a royalty-free codec currently being developed in MPEG. Coding efficiency of IVC codec has been steadily enhanced and it was reported that the performance of Committee Draft (CD) version is comparable to H.264/AVC High Profile (HP) in terms of objective and subjective qualities. In this paper, we present some coding tools that have been proposed for enhancing the coding efficiency of IVC during the developing process in MPEG along with brief overview of IVC codec architecture and coding algorithms. The coding tools include both of normative tools and informative tools such as non-reference P frame coding, DC mode intra prediction, Lagrange multiplier selection, and extension of chroma intra prediction modes. Improvement obtained by each tool is presented in terms of algorithm and coding gain based on the experiments. As a result of the experiment, the coding tools give the average bit saving of 8.8%, 0.4%, 0.4%, and 0.0%, respectively, in the low-delay coding mode.

• The Journal of the Korea institute of electronic communication sciences
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• v.15 no.5
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• pp.827-834
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• 2020

In this paper, a third-order harmonic mixer is designed using frequency multiplier theory for the microwave airborne radar. Unlike the basic mixer design method, the gate bias voltage, at which the third-harmonic component of the Local frequency (LO) is the maximum, is selected using a frequency multiplier theory to maximize the third-harmonic mixing component at the intermediate frequency (IF). The proposed harmonic mixer was designed and manufactured using a commercial GaAs MESFET device in a plastic package, and it was possible to improve the high conversion loss, circuit complexity, high cost, and manufacturing complexity of the existing microwave mixer. The harmonic mixer using the proposed design method has a -8 ~ -10 dB conversion loss by pumping 11.5 GHz LO with a +5 dBm level when operating from 33.0 GHz to 36.0 GHz and the 1-dB gain compression point (P1dB) of 0 dBm.

• Journal of the Korean Society of Safety
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• v.24 no.2
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• pp.83-88
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• 2009

The objective of this paper was to evaluate the effectiveness of horizontal, vertical, asymmetric and coupling multipliers for manual material handling. Lifting tasks with 5 different horizontal distances ($30{\sim}70cm$) for 6 vertical distances(ankle, knee, waist, elbow, shoulder and head height) were experimented. The muscle activity and muscle exertion level during asymmetric load handling(without trunk flexion) was experimented. Lifting tasks with and without handle tote box for three postures(straight, bending, right angle posture) were experimented. The degrading tendency did not appeared almost in $60{\sim}70cm$ interval's horizontal distance. As a result of ANOVA, MVC paid attention to horizontal and vertical distance but cross effect was insignificant(p<0.01). The change of the MVC according to the horizontal, vertical distance appeared similar from of RWL. The results of normalized MVC measurement were decreased about 16%, 24%, 34% respectively as the asymmetry angle was $30^{\circ}$, $60^{\circ}$, $90^{\circ}$. RMS EMG values of right erector spinae muscles were decreased as the work posture went to $90^{\circ}$ and those of left erector spinae muscles were increased until the asymmetry angle was $40^{\circ}$ but decreased continually over $40^{\circ}$. 7 subjects, activities of left and right latissimus dorsi muscles were maintained constantly, while for remainer, those were irregular. MVC reduced maximum 23% by type of handle. MVC was highest in straight posture, but was lowest in right angle posture. As a result of ANOVA, MVC paid attention to posture, coupling(p<0.01). To all handle types, biceps brachii activity was increased in right angle posture, but reduced in straight posture. Based on the results of this study, it is suggested that the NIOSH guideline should not be directly applied to Korean without reasonable reexamination. In addition, we need to afterward study through an age classification.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.12
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• pp.1882-1889
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• 2021

This paper describes a high-performance hardware implementation of modular multiplication used as a core operation in elliptic curve cryptography. A 521-bit high-performance modular multiplier for NIST P-521 curve was designed by adopting 3-way Toom-Cook integer multiplication and fast reduction algorithm. Considering the property of the 3-way Toom-Cook algorithm in which the result of integer multiplication is multiplied by 1/3, modular multiplication was implemented on the Toom-Cook domain where the operands were multiplied by 3. The modular multiplier was implemented in the xczu7ev FPGA device to verify its hardware operation, and hardware resources of 69,958 LUTs, 4,991 flip-flops, and 101 DSP blocks were used. The maximum operating frequency on the Zynq7 FPGA device was 50 MHz, and it was estimated that about 4.16 million modular multiplications per second could be achieved.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.585-586
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• 2008

In this paper, a novel beta-multiplier reference current source circuit for the 800mV power-supply voltage is presented. In order to cope with the narrow input common-mode range of the OpAmp in the reference circuit, shunt resistive voltage divider branches were deployed. High gain OpAmp was designed to compensate intrinsic low output resistance of the MOS transistors. The proposed reference circuit was designed in a standard 0.18um CMOS process with nominal Vth of 420mV and -450mV for nMOS and pMOS transistor respectively. The total power consumption including OpAmp is less than 50uW.