• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.11a
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• pp.210-215
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• 1994

In the CMOS device, Counter doping is needed to adjust threshold voltage because of the difference between n-MOSFET and p-MOSFET well doping concentration when n+ polysilicon gate is used. Therefore buried channel is formed in the p-channel MOSFET degrading properties. So well doping concentration and doping condition should be considered in fabrication process and device design. Here we are to extract the initial process condition using simulation and fabricate p-MOSFET device and then compare the subthreshold characteristics of simulated and fabricated device.

• Journal of Sensor Science and Technology
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• v.8 no.5
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• pp.421-426
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• 1999

In this paper, we present p-channel GaAs MOSFET having $Al_2O_3$ as gate insulator fabricated on a semi-insulating GaAs substrate, which can be operated in the depletion mode. $1\;{\mu}m$ thick undoped GaAs buffer layer, $4000\;{\AA}$ thick p-type GaAs epi-layer, undoped $500{\AA}$ thick AlAs layer, and $50\;{\AA}$ thick GaAs cap layer were subsequently grown by molecular beam epitaxy(MBE) on (100) oriented semi-insulating GaAs substrate and this wafer was oxidized. AlAs layer was fully oxidized as a $Al_2O_3$ thin film. The I-V, $g_m$, breakdown charateristics of the fabricated GaAs MOSFET showed that wet thermal oxidation of AlAs/GaAs epilayer/S I GaAs was successful in realizing depletion mode p-channel GaAs MOSFET.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.21-27
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• 2009

In this work, Er-silicided SB-SOI nMOSFET and Pt-silicided SB-SOI pMOSFET have been fabricated to investigate the current-voltage characteristics of Schottky barrier SOI nMOS and pMOS at elevated temperature. The dominant current transport mechanism of SB nMOS and pMOS is discussed using the measurement results of the temperature dependence of drain current with gate voltages. It is observed that the drain current increases with the increase of operating temperature at low gate voltage due to the increase of thermal emission and tunneling current. But the drain current is decreased at high gate voltage due to the decrease of the drift current. It is observed that the ON/Off current ratio is decreased due to the increased tunneling current from the drain to channel region although the ON current is increased at elevated temperature. The threshold voltage variation with temperature is smaller and the subthreshold swing is larger in SB-SOI nMOS and pMOS than in SOI devices or in bulk MOSFETs.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.457-460
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• 1998

단 채널 MOSFET 소자의 드레인 전압-드레인 전류 특성을 예측하기 위해서 caughey-thomas 이동도 모델을 수치적으로 구현하는 방법을 제안한다. 구현된 caughey-thomas 모델의 정확한 특성을 검증하기 위해서 0.5[.mu.m]의 설계규칙을 가즌 ASIC용 공정으로 n-MOSFET과 p-MOSFET을 제작하였다. 전자 및 정공의 포화속도 값이 각각 6.2*10/sup 6/[cm/sec] 과 1.034*10/sup 7/[cm/sec]인 경우에 채널길이가 0.5[.mu.m] 이상인 n-MOSFET과 p-MOSFET의 드레인 전압-드레인 전류특성의 모의실험 결과는 측정값에 비하여 10% 이내의 상대오차를 보였다.

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.430-432
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• 2005

저에너지 중성자가 가톨리늄(Gd) 막에 입사되면 중성자 포획과정에서 전환전자가 생성된다. 이 전환전자에 의해 pMOSFET $SiO_2$ 산화층에서 발생된 전자-전공쌍이 발생되고, 이 가운데 정공은 산화층 내부에 쉽게 붙잡혀(Trap) 양전하 센터로 작용하게 된다. 이 축적된 전하는 pMOSFET의 문턱전압(Threshold voltage)을 변화시킨다. 본 연구에서는 이러한 간접측정 원리를 이용하여 열중성자를 실기간 탐지할 수 있는 반도체형 탐지소자를 개발하고 하나로(HANARO) 방사선장에서의 시험을 통해 성능을 검증하였다. 그리고 감도관련 변수의 최적화를 통하여 작업자가 사용 가능한 범위의 고감도 열중성자 선량계로 개선 제작하였다. 개발된 선량계는 소형으로 실시간 열중성자 측정이 가능하며 감마방사선으로부터 독립적으로 열중성자를 측정할 수 있는 장점도 지니고 있다.

• ETRI Journal
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• v.9 no.1
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• pp.118-124
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• 1987

Short channel n-MOSFET의 드레인-소오스 사이의 breakdown은 단순한 접합 breakdown이 아닌 avalanche-induced breakdown으로 p-MOSFET, long channel n-MOSFET의 breakdown 전압보다 훨씬 작은 값을 갖는다. Short channel n-MOSFET의 breakdown의 특징은 current-controlled 부저항 특성(snapback)이 나타나고, 게이트 전압에 따라 breakdown 전압보다 작은 sustainning 전압이 존재한다. 이와 같은 sustainning 전압은 short channel n-MOSFET의 안정한 동작에 또 하나의 제한 요소가 될 수 있다. 따라서 공정 및 회로 시뮬레이션을 위해, short channel n-MOSFET의 avalanche breakdown 현상에 대한 정확한 분석이 요구된다. Short channel n -MOSFET의 avalanche breakdown 현상을 분석하기 위해서Parasitic bipolar transistor를 도입한 분석적 모델을 이용하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.8
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• pp.497-500
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• 2014

In this paper, we analyze electrical characteristics of n/p-pillar layer according to trench angle which is the most important characteristics of SJ MOSFET and core process. Because research target is 600 V class SJ MOSFET, so conclusively trench angle deduced 89.5 degree to implement the breakdown voltage 750 V with 30% margin rate. we found that on resistance is $22mohm{\cdot}cm^2$ and threshold voltage is 3.5 V. Moreover, depletion layer of electric field distribution also uniformly distributes.

• Journal of Sensor Science and Technology
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• v.9 no.3
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• pp.213-223
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• 2000

It is necessary that radiation dose would be detect exactly generated from facility related to nuclear, space, radiotherapy center, etc. This paper is to use of the radiation-induced threshold voltage change as an accumulated radiation dose monitoring sensor. Commercial P Channel Power MOSFET(metal oxide field effect transistor) were tested in a Co-60 gamma irradiation facility to see their capabilities as a radiation dosimeter. We found that the transistors showed good linearity in their threshold voltage shift characteristics with radiation dose. The results demonstrate the potential use of commercial P Channel Power MOSFET as inexpensive radiation sensors.

• Journal of IKEEE
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• v.18 no.4
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• pp.532-535
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• 2014

This paper analyzed thermal characteristics of super junction MOSFET using process and design parameters. Trench process is very important to super junction MOSFET process. We analyzed the difference of temperature, thermal resistance, total power consumption according to trench etch angle. As a result we obtained minimum value of temperature difference and thermal resistance at $89.3^{\circ}$ of trench etch angle. The electrical characteristics distribution of super junction MOSFET is not showed tendency according to trench etch angle. We need iterative experiments and simulation for optimal value of electrical characteristics. The super junction power MOSFET that has superior thermal characteristics will use automobile and industry.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.3
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• pp.540-544
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• 2017

In this study, we analyzed the effects of TID(Total Ionizing Dese) and TREE(Transient Radiation Effects on Electronics) on nMOSFET and pMOSFET fabricated by 0.18um CMOS process. The size of nMOSFET and pMOSFET is 100um/1um(W/L). The TID test was conducted up to 1 Mrad(Si) with a gamma-ray(Co-60). During the TID test, the nMOSFET generated leakage current proportional to the applied dose, but that of the pMOSFET was remained in a steady state. The TREE test was conducted at TEST LINAC in Pohang Accelerator Laboratory with a maximum dose-rate of $3.16{\times}10^8rad(si)/s$. In that test nMOESFET generated a large amount of photocurrent at a maximum of $3.16{\times}10^8rad(si)/s$. Whereas, pMOSFETs showed high TREE immunity with a little amount of photocurrent at the same dose rate. Based on the results of this experiment, we will progress the research of the radiation hardening for CMOS unit devices.