• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04b
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• pp.43-46
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• 2000

In this paper, the stress and transient currents associated with the on and off time of applied voltage were used to measure the density and distribution of high voltage stress induced traps in thin silicon oxide films. The transient currents were due to the discharging of traps generated by high stress voltage in the silicon oxides. The trap distributions were relatively uniform near both cathode and anode interface. The trap densities were dependent on the stress polarity. The stress generated trap distributions were relatively uniform the order of $10^{11}\sim10^{21}$[states/eV/$cm^2$] after a stress. The trap densities at the oxide silicon interface after high stress voltages were in the $10^{10}\sim10^{13}$[states/eV/$cm^2$]. It appear that the stress and transient current that flowed when the stress voltage were applied to the oxide was caused by carriers tunneling through the silicon oxide by the high voltage stress generated traps.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.2
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• pp.17-24
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• 2000

In this paper, the stress and transient currents associated with the on and off time of applied voltage were used to measure the density and distribution of high voltage stress induced traps in thin silicon oxide films. The transient currents were due to the discharging of traps generated by high stress voltage in the silicon oxides. The trap distributions were relatively uniform new both cathode and anode interface. The trap densities were dependent on the stress polarity. The stress generated trap distributions were relatively uniform the order of 1011~1021[states/eV/cm2] after a stress voltage. It appear that the stress and transient current that flowed when the stress voltage were applied to the oxide was caused by carriers tunneling through the silicon oxide by the high voltage stress generated traps.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.453-456
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• 1999

The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor)NVSM(nonvolatile semiconductor memory) cell were investigated by single charge pumping method. The used device was fabricated by 0.35 7m standard logic fabrication including the ONO cell process. This ONO dielectric thickness is tunnel oxide 24 $\AA$, nitride 74 $\AA$, blocking oxide 25 $\AA$, respectively. Keeping the pulse base level in accumulation and pulsing the surface into inversion with increasing amplitudes, the charge pumping current flow from the single junction. Using the obtained I$_{cp}$-V$_{h}$ curve, the local V$_{t}$ distribution, doping concentration, lateral interface trap distribution and lateral memory trap distribution were extracted. The maximum N$_{it}$($\chi$) of 1.62$\times$10$^{19}$ /cm$^2$were determined.mined.d.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.10 no.6
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• pp.412-417
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• 2000

High electric field stressed trap distributions were investigated in the thin silicon oxide of polycrystalline silicon gate metal oxide semiconductor capacitors. The transient currents associated with the off time of stressed voltage were used to measure the density and distribution of high voltage stress induced traps. The transient currents were due to the discharging of traps generated by high stress voltage in the silicon oxides. The trap distributions were relatively uniform near both cathode and anode interface in polycrystalline silicon gate metal oxide semiconductor devices. The stress generated trap distributions were relatively uniform the order of $10^{11}$~$10^{12}$ [states/eV/$\textrm{cm}^2$] after a stress. The trap densities at the oxide silicon interface after high stress voltages were in the $10^{10}$~$10^{13}$ [states/eV/$\textrm{cm}^2$]. It was appeared that the transient current that flowed when the stress voltages were applied to the oxide was caused by carriers tunneling through the silicon oxide by the high voltage stress generated traps.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.8
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• pp.56-62
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• 1992

This paper is analyzed the charge trapping and electrical properties of 0(Oxide), NO(Nitrided oxide) and ONO(Reoxidized nitrided oxide) as dielectric films in MIS structures. We have processed bottom oxide and top oxide by the thermal method, and nitride(Si$_{3}N_{4}$) by the LPCVD(Low Pressure Chemical Vapor Deposition) method on P-type(100) Silicon wafer. We have studied the charge trapping properties of the dielectrics by using a computer controlled DLTS system. All of the dielectric films are shown peak nearly at 300K. Those are bulk traps. Many trap densities which is detected in NO films, but traps. Many trap densities which is detected in NO films. Varing the nitride thickness, the trap densities of thinner nitride is decreased than the thicker nitride. Finally we have found that trap densities of ONO films is affected by nitride thickness.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.575-578
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• 2002

In this paper, we discuss carrier trapping model and trap characteristics of nitrided oxide thin film. Based on the experimental results, the carrier trapping model for system having multi-traps is proposed and is fitted with experimental data in order to determine trap parameter of nitride oxide and O2 annealed nitrided oxide. As a results of curve fitting, the heavy nitridation of oxide introduces three kinds of traps with capture cross section $\sigma$n1=1.48$\times$10$^{-17}$ $\textrm{cm}^2$, $\sigma$n2=1.51$\times$10$^{-19}$ $\textrm{cm}^2$, $\sigma$p=1.53$\times$10$^{-18}$ $\textrm{cm}^2$ and corresponding trap densities Nnl=2.66$\times$10$^{12}$ Cm$^{-2}$ , Nn2=1.32$\times$10$^{12}$ Cm$^{-2}$ , Np=8.35$\times$10$^{12}$ Cm$^{-2}$ .

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.310-310
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• 2016

최근 NAND flash memory는 높은 집적성과 데이터의 비휘발성, 낮은 소비전력, 간단한 입, 출력 등의 장점들로 인해 핸드폰, MP3, USB 등의 휴대용 저장 장치 및 노트북 시장에서 많이 이용되어 왔다. 특히, 최근에는 smart watch, wearable device등과 같은 차세대 디스플레이 소자에 대한 관심이 증가함에 따라 유연하고 투명한 메모리 소자에 대한 연구가 다양하게 진행되고 있다. 대표적인 플래시 메모리 소자의 구조로 charge trapping type flash memory (CTF)가 있다. CTF 메모리 소자는 trap layer의 trap site를 이용하여 메모리 동작을 하는 소자이다. 하지만 작은 window의 크기, trap site의 열화로 인해 메모리 특성이 나빠지는 문제점 등이 있다. 따라서 최근, trap layer에 다양한 물질을 적용하여 CTF 소자의 문제점을 해결하고자 하는 연구들이 진행되고 있다. 특히, 산화물 반도체인 zinc oxide (ZnO)를 trap layer로 하는 CTF 메모리 소자가 최근 몇몇 보고 되었다. 산화물 반도체인 ZnO는 n-type 반도체이며, shallow와 deep trap site를 동시에 가지고 있는 독특한 물질이다. 이 특성으로 인해 메모리 소자의 programming 시에는 deep trap site에 charging이 일어나고, erasing 시에는 shallow trap site에 캐리어들이 쉽게 공급되면서 deep trap site에 갇혀있던 charge가 쉽게 de-trapped 된다는 장점을 가지고 있다. 따라서, 본 실험에서는 산화물 반도체인 ZnO를 trap layer로 하는 CTF 소자의 메모리 특성을 확인하기 위해 간단한 구조인 metal-oxide capacitor (MOSCAP)구조로 제작하여 메모리 특성을 평가하였다. 먼저, RCA cleaning 처리된 n-Si bulk 기판 위에 tunnel layer인 SiO2 5 nm를 rf sputter로 증착한 후 furnace 장비를 이용하여 forming gas annealing을 $450^{\circ}C$에서 실시하였다. 그 후 ZnO를 20 nm, SiO2를 30 nm rf sputter로 증착한 후, 상부전극을 E-beam evaporator 장비를 사용하여 Al 150 nm를 증착하였다. 제작된 소자의 신뢰성 및 내구성 평가를 위해 상온에서 retention과 endurance 측정을 진행하였다. 상온에서의 endurance 측정결과 1000 cycles에서 약 19.08%의 charge loss를 보였으며, Retention 측정결과, 10년 후 약 33.57%의 charge loss를 보여 좋은 메모리 특성을 가지는 것을 확인하였다. 본 실험 결과를 바탕으로, 차세대 메모리 시장에서 trap layer 물질로 산화물 반도체를 사용하는 CTF의 연구 및 계발, 활용가치가 높을 것으로 기대된다.

• Korean Journal of Materials Research
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• v.19 no.9
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• pp.462-467
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• 2009

The Charge Trap Flash (CTF) memory device is a replacement candidate for the NAND Flash device. In this study, Pt/$Al_2O_3/La_2O_3/SiO_2$/Si multilayer structures with lanthanum oxide charge trap layers were fabricated for nonvolatile memory device applications. Aluminum oxide films were used as blocking oxides for low power consumption in program/erase operations and reduced charge transports through blocking oxide layers. The thicknesses of $SiO_2$ were from 30 $\AA$ to 50 $\AA$. From the C-V measurement, the largest memory window of 1.3V was obtained in the 40 $\AA$ tunnel oxide specimen, and the 50 $\AA$ tunnel oxide specimen showed the smallest memory window. In the cycling test for reliability, the 30 $\AA$ tunnel oxide sample showed an abrupt memory window reduction due to a high electric field of 9$\sim$10MV/cm through the tunnel oxide while the other samples showed less than a 10% loss of memory window for $10^4$ cycles of program/erase operation. The I-V measurement data of the capacitor structures indicated leakage current values in the order of $10^{-4}A/cm^2$ at 1V. These values are small enough to be used in nonvolatile memory devices, and the sample with tunnel oxide formed at $850^{\circ}C$ showed superior memory characteristics compared to the sample with $750^{\circ}C$ tunnel oxide due to higher concentration of trap sites at the interface region originating from the rough interface.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.8
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• pp.59-63
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• 2015

This paper discusses the capacitance-voltage method in Metal-Oxide-Nitride-Oxide-Silicon (MONOS) devices to analyzed the characteristics of the top oxide/nitride, nitride/bottom oxide interface trap distribution. In the CV method, nitride trap density can be calculated based on the program characteristics of the nitride thickness variations. By applying this method, silicon rich nitride device found to have a larger trap density than stoichiometric nitride device. This result is consistent with previous studies. If this comparison analysis can be expected to result in improved reliability of the SONOS flash memory.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.1
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• pp.13-18
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• 1999

The trap density by the stress bias in silicon oxides with different thicknesses has been investigated. The trap density by stress bias was shown to be composed of on time current and off time current. The on time trap density was composed of dc current. The off time trap density was caused by the tunneling charging and discharging of the trap in the interfaces. The on time trap density was used to estimate to the limitations on oxide thicknesses. The off time trap density was used to estimate the data retention in nonvolatile memory devices.