• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.409-409
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• 2011

All solid-state thin film lithium batteries have many applications in miniaturized devices because of lightweight, long-life, low self-discharge and high energy density. The research of cathode materials for thin film lithium batteries that provide high energy density at fast discharge rates is important to meet the demands for high-power applications. Among cathode materials, lithium manganese oxide materials as spinel-based compounds have been reported to possess specific advantages of high electrochemical potential, high abundant, low cost, and low toxicity. However, the lithium manganese oxide has problem of capacity fade which caused by dissolution of Mn ions during intercalation reaction and phase instability. For this problem, many studies on effect of various transition metals have been reported. In the preliminary study, the Sn-substituted LiMn2O4 thin films prepared by pulsed laser deposition have shown the improvement in discharge capacity and cycleability. In this study, the thin films of LiMn2O4 and LiSn0.0125Mn1.975O4 prepared by RF magnetron sputtering were studied with effect of deposition parameters on the phase, surface morphology and electrochemical property. And, all solid-state thin film batteries comprised of a lithium anode, lithium phosphorus oxy-nitride (LiPON) solid electrolyte and LiMn2O4-based cathode were fabricated, and the electrochemical property was investigated.

• Journal of Sensor Science and Technology
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• v.4 no.1
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• pp.3-8
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• 1995

n-ITO/p-PSL heterojunction photodetector have been fabricated on the Si wafer by using ITO(indium tin oxide) and PSL(porous silicon layer). They were anodized selectively by using silicon nitride and Ni-Cr/Au and were passivated by using ITO as well as being isolated by using mesa structure. With white light from 0 to 3000 Lux, the photocurrent varied linearly with incident light intensity. The reverse characteristics of fabricated devices were very stable up to a bias voltage of -40V and dark current density was about $40nA/mm^{2}$. When the device was exposed by Xe lamp whose wavelength range from 400nm to 1100nm, the maximum photo responsivity was about 0.6A/W between 600 and 700nm. Variation of the characteristics of fabricated devices after 5 weeks was negligible.

• Journal of the Korean Ceramic Society
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• v.20 no.3
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• pp.211-216
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• 1983

This work aims at characterizing silicon grains and its compacts. In order to remove iron silicon grains were washed with 5N hydrochloride at 60-7$0^{\circ}C$ for 170 hrs, and then followed the chemical analysis by atomic absorption spectrophotometer X-ray diffraction analysis SEM observation and specific surface area determination by B. E. T. Mixtures of graded silicon particles with two or three different sizes were made into packings by mechanical vibration. The mixtures were used to make compacts with 10 mm in diameter and 70mm in length by isostatically pressing at 1, 208 kg/$cm^2$ (20 kpsi) and 4, 255kg/$cm^2$ (60 kpsi) respectively. Bulk densities of packings and compacts were measured. A slip made of magnesium nitrate solution and fine silicon particles was spray-dried and then decomposed at 30$0^{\circ}C$ for the purpose of coating the uniform layer of magnesium oxide on the surface of particles. The results obtained are as follows: (1) About two thirds of iron content could be removed from silicon by washing silicon powders with hydrochloride. (2) Uniform layer of magnesium oxide on the surface of silicon could be prepared by spray-drying suspension and by decomposing it. (3) B. E. T. specific surface area of fine silicon particles was 2, 826.753$m^3$/kg. (4) In the binary system with two sizes of 40-53$\mu\textrm{m}$ particles and <10$\mu\textrm{m}$ particles the maximum bulk density of packing was 55% of theoretical value and that of compacts made at the pressure of 4, 255 kg./$cm^2$ (60 kpsi) was 73% of theoretical value. (5) In the ternary system with three sizes the maximum bulk density of packing was 1.43 g/$cm^3$and that of compacts was 1.80g/$cm^3$which is equivalent to 77.6% of theoretical value. The composition of the closest compact was consisted of 50% of 40-53$\mu\textrm{m}$ particles 20% of 10-30$\mu\textrm{m}$ particles and 30% of <10$\mu\textrm{m}$ parti-cles.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.35-38
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• 2002

In this paper, the characteristics of channel hot electron (CHE) injection for the write operation in a NOR-type SONOS flash memory with common source line were investigated. The thicknesses of he tunnel oxide, the memory nitride， and the blocking oxide layers for the gate insulator of the fabricated SONOS devices were $34{\AA}$, $73{\AA}$, and $34{\AA}$, respectively. The SONOS devices compared to floating gate devices have many advantages, which are a simpler cell structure, compatibility with conventional logic CMOS process and a superior scalability. For these reasons, the introduction of SONOS device has stimulated. In the conventional SONOS devices, Modified Folwer-Nordheim (MFN) tunneling and CHE injection for writing require high voltages, which are typically in the range of 9 V to 15 V. However CHE injection in our devices was achieved with the single power supply of 5 V. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve were investigated. The memory window of about 3.2 V and the write speed of $100{\mu}s$ were obtained. Also, the disturbance and drain turn-on leakage during CHE injection were not affected in the SONOS array. These results show that CHE injection can be achieved with a low voltage and single power supply, and applied for the high speed program of the SONOS memory devices.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.1268-1270
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• 1993

In this study, the characteristics of Si-$SiO_2$ interface and its degradation in short channel SONOSFET nonvolatile memory devices, fabricated by 1Mbit CMOS process($1.2{\mu}m$ design rule), with $65{\AA}$ blocking oxide layer, $205{\AA}$ nitride layer, and $30{\AA}$ tunneling oxide layer on the silicon wafer were investigated using the charge pumping method. For investigating the Si-$SiO_2$ interface characteristics before and after write/erase cycling, charge pumping current characteristics with frequencies, write/erase cycles, as a parameters, were measured. As a result, average Si-$SiO_2$ interface trap density and mean value of capture cross section were determined to be $1.203{\times}10^{11}cm^{-2}eV^{-1}\;and\;2.091{\times}10^{16}cm^2$ before write/erase cycling, respectively. After cycling, when the write/erase cycles are $10^4$, average $Si-SiO_2$ interface trap density was $1.901{\times}10^{11}cm^{-2}eV^{-1}$. Incresing write/erase cycles beyond about $10^4$, Si-$SiO_2$ interface characteristics with write/erase cycles was increased logarithmically.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.6
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• pp.445-449
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• 2020

Non-volatile memory is approaching its fundamental limits with the Si₃N₄ storage layer, necessitating the use of alternative materials to achieve a higher programming/erasing speed, larger storage window, and better data retention at lower operating voltage. This limitation has restricted the development of the charge-trap memory, but can be addressed by using high-k dielectrics. The paper reviews the doping of nitrogen, titanium, and yttrium on high-k dielectrics as a storage layer by comparing MONOS devices with different storage layers. The results show that nitrogen doping increases the storage window of the Gd₂O₃ storage layer and improves its charge retention. Titanium doping can increase the charge capture rate of HfO₂ storage layer. Yttrium doping increases the storage window of the BaTiO₃ storage layer and improves its fatigue characteristics. Parameters such as the dielectric constant, leakage current, and speed of the memory device can be controlled by maintaining a suitable amount of external impurities in the device.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.209-209
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• 2010

단위면적 당 메모리 집적도를 높이기 위해 플래시 기억소자의 크기를 줄일 때, 절연층 두께 감소에 의한 누설 전류의 발생, 단채널 효과 및 협폭 효과와 같은 문제 때문에 소자 크기의 축소가 한계에 도달하고 있다. 이러한 문제점들을 개선하기 위해 본 연구에서는 FinFET구조위에 Oxide-Nitride-Oxide (ONO) 층을 적층하여 2-비트 특성을 갖는 플래시 메모리 소자를 제안하였다. 소자의 작동전압을 크게 줄일 수 있으며 소자의 크기가 작아질 때 일어나는 단채널 효과의 문제점을 해결할 수 있는 FinFET 구조를 가진 기억소자에서 제어게이트를 제어게이트1과 제어게이트2로 나누어 독립적으로 쓰기 및 소거 동작하도록 하였다. 2-비트 동작을 위해 제어 게이트1의 게이트 절연막의 두께를 제어게이트2의 게이트 절연막의 두께보다 더 얇게 함으로써 두 제어게이트 사이의 coupling ratio를 다르게 하였다. 제어게이트1의 트랩층의 두께를 제어게이트2의 트랩층의 두께보다 크게 하여 제어게이트1의 트랩층에 더 많은 양의 전하가 포획될 수 있도록 하였다. 제안한 기억소자가 2-비트 동작하는 것을 확인 하기위하여 2차원 시뮬레이션툴인 MEDICI를 사용하여 제시한 FinFET 구조를 가진 기억소자의 전기적 특성을 시뮬레이션하였다. 시뮬레이션을 통해 얻은 2-비트에 대한 각 상태에서 각 전하 포획 층에 포획된 전하량의 비교를 통해서 coupling ratio 차이와 전하 포획층의 두께 차이로 인해 포획되는 전하량이 달라졌다. 각 상태에서 제어게이트에 읽기 전압을 인가하여 전류-전압 특성 곡선을 얻었으며, 각 상태에서의 문턱전압들이 잘 구분됨을 확인함으로써 제안한 FinFET 구조를 가진 플래시 메모리 소자가 셀 당 2-비트 동작됨을 알 수 있었다.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.109-109
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• 2010

$Er^{3+}$ ion shows a stable and efficient luminescence at 1.54mm due to its $^4I_{13/2}\;{\rightarrow}\;^4I_{15/2}$ intra-4f transition. As this corresponds to the low-loss window of silica-based optical fibers, Er-based light sources have become a mainstay of the long-distance telecom. In most telecom applications, $Er^{3+}$ ions are excited via resonant optical pumping. However, if nanocluster-Si (nc-Si) are co-doped with $Er^{3+}$, $Er^{3+}$ can be excited via energy transfer from excited electrical carriers in the nc-Si as well. This combines the broad, strong absorption band of nc-Si with narrow, stable emission spectra of $Er^{3+}$ to allow top-pumping with off-resonant, low-cost broadband light sources as well as electrical pumping. A widely used method to achieve nc-Si sensitization of $Er^{3+}$ is high-temperature annealing of Er-doped, non-stoichiometric amorphous thin film with excess Si (e.g.,silicon-rich silicon oxide(SRSO)) to precipitate nc-Si and optically activate $Er^{3+}$ at the same time. Unfortunately, such precipitation and growth of nc-Si into Er-doped oxide matrix can lead to $Er^{3+}$ clustering away from nc-Si at anneal temperatures much lower than ${\sim}1000^{\circ}C$ that is necessary for full optical activation of $Er^{3+}$ in $SiO_2$. Recently, silicon-rich silicon nitride (SRSN) was reported to be a promising alternative to SRSO that can overcome this problem of Er clustering. But as nc-Si formation and optical activation $Er^{3+}$ remain linked in Er-doped SRSN, it is not clear which mechanism is responsible for the observed improvement. In this paper, we report on investigating the effect of separating the nc-Si formation and $Er^{3+}$ activation by using hetero-multilayers that consist of nm-thin SRSO or SRSN sensitizing layers with Er-doped $SiO_2$ or $Si_3N_4$ luminescing layers.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.6
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• pp.1175-1180
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• 2022

STI has been studied a lot as a process technology for wide area planarization according to miniaturization and high integration of semiconductor devices. In this study, as methods for improving the STI profile, wet etching of pad oxide using hydrofluorine solution and dry etching of O₂+CF₄ after STI dry etching were proposed. This process technology showed improvement in profile imbalance and leakage current between patterns according to device density compared to the conventional method. In addition, as a result of measuring the HLD thickness after CMP for a device having the same STI depth and HLD deposition, the measured value was different depending on the device density. It was confirmed that this was due to the difference in the thickness of the nitride film according to the device density after CMP and the selectivity of the slurry.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.2
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• pp.43-51
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• 2023

In this paper, we introduce the development trends of power devices which is the key component for power conversion system in electric vehicles, and discuss the characteristics of the next-generation wide-bandgap (WBG) power devices. We provide an overview of the characteristics of the present mainstream Si insulated gate bipolar transistor (IGBT) devices and technology roadmap of Si IGBT by different manufacturers. Next, recent progress and advantages of SiC metal-oxide-semiconductor field-effect transistor (MOSFET) which are the most important unipolar devices, is described compared with conventional Si IGBT. Furthermore, due to the limitations of the current GaN power device technology, the issues encountered in applying the power conversion module for electric vehicles were described.