• The Journal of Korean Physical Therapy
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• 제27권1호
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• pp.38-42
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• 2015

Purpose: Accuracy and variability of movement in daily life require synchronization of muscular activities through a specific chronological order of motor performance, which is controlled by higher neural substrates and/or lower motor centers. We attempted to investigate whether transcranial direct current stimulation (tDCS) over primary sensorimotor areas (SM1) could influence movement variability in healthy subjects, using a tapping task. Methods: Twenty six right-handed healthy subjects with no neurological or psychiatric disorders participated in this study. They were randomly and equally assigned to the real tDCS group or sham control group. Direct current with intensity of 1 mA was delivered over their right SM1 for 15 minutes. For estimation of movement variability before and after tDCS, tapping task was measured, and variability was calculated as standard deviation of the inter-tap interval (SD-ITI). Results: At the baseline test, there was no significant difference in SD-ITI between the two groups. In two-way ANOVA with repeated measurement no significant differences were found in a large main effect of group and interaction effect between two main factors (i.e., group factor and time factor (pre-post test)). However, significant findings were observed in a large main effect of the pre-post test. Conclusion: Our findings showed that the anodal tDCS over SM1 for 15 minutes with intensity of 1 mA could enhance consistency of motor execution in a repetitive-simple tapping task. We suggest that tDCS has potential as an adjuvant brain facilitator for improving rhythm and consistency of movement in healthy individuals.

• Physical Therapy Rehabilitation Science
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• 제11권1호
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• pp.8-15
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• 2022

Objective: Post stroke motor recovery is facilitated by the brain reorganization or the neuroplastic changes. The therapeutic approach mentioned in the current case is one of the approaches for enhancing motor recovery by stimulating the damaged neural networks directing the motor behaviour of a person. The aim of the present study was to establish the changes in the balance and gait pattern of an individual through multi target stimulation of areas of cerebral cortex by utilising multichannel trans cranial direct current stimulation (M-tDCS) in a sub-acute stroke survivor. Design: A Case Report Methods: The present patient was the participant of the trial (CTRI/2021/02/031044).The patient was intervened with M-tDCS (anodes over left primary motor cortex that is C3 point and left dorsolateral prefrontal cortex i.e., F3 point and cathodes over supraorbital areas, Intensity - 1.2mA) for the duration of 20 minutes along with turbo med extern - an AFO to facilitate ankle dorsi flexion and conventional physiotherapy rehabilitation. The Fugl-Meyer assessment lower extremity (FMA-LE), Berg Balance Scale (BBS), Wisconsin Gait Scale (WGS) and the Stroke Specific Quality of Life (SSQOL) measures were used for outcome assessment. Baseline assessment was done on day 0 followed by assessment on 10 and 20 post intervention. Results: Improvement was seen in all the tools i.e. (FMA -LE), BBS, SSQOL and WGS over the time period of 20 days. Conclusions: M-tDCS resulted in improvement in gait parameters, balance and motor functions of lower extremity of the patient.

• 대한전기학회논문지:전력기술부문A
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• 제55권3호
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• pp.95-101
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• 2006

This paper proposes a modified current differential relay for $Y-{\Delta}$ transformer protection. The relay uses the same restraining current as a conventional relay, but the differential current is modified to compensate for the effects of the exciting current. A method to estimate the circulating component of the delta winding current is proposed. To cope with the remanent flux, before saturation, the core-loss current is calculated and used to modify the measured differential current. When the core then enters saturation, the initial value of the flux is obtained by inserting the modified differential current at the start of saturation into the magnetization cure. Thereafter, the core flux is then derived and used in conjunction with the magnetization curve to calculate the magnetizing current. A modified differential current is then derived that compensates for the core-loss and magnetizing currents. The performance of the proposed differential relay was compared against a conventional differential relay. Test results indicate that the modified relay remained stable during severe magnetic inrush and over-excitation, because the exciting current was successfully compensated. This paper concludes by implementing the relay on a hardware platform based on a digital signal processor. The relay does not require additional restraining signal and thus cause time delay of the relay.

• Journal of Power Electronics
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• 제17권6호
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• pp.1672-1682
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• 2017

For grid-connected LCL-filtered inverters, the inverter-side current can be used as the control object with one current sensor for both LCL resonance damping and over-current protection, while the grid-voltage feedforward or harmonic resonant compensator is used for suppressing low-order grid current harmonics. However, it was found that the grid current harmonics were high and often beyond the standard limitations with this control. The limitations of the inverter-side current control in suppressing low-order grid current harmonics are analyzed through inverter output impedance modeling. No matter which compensator is used, the maximum magnitudes of the inverter output impedance at lower frequencies are closely related to the LCL parameters and are decreased by increasing the control delay. Then, to improve the grid current quality without complicating the control or design, this study proposes designing the filter capacitance considering the current harmonic constraint and using a PWM mode with a short control delay. Test results have confirmed the limitation and verified the performance of the improved approaches.

• 한국전기전자재료학회논문지
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• 제23권8호
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• pp.593-600
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• 2010

In this paper, High brightness LED (light-emitting diodes) driver IC (integrated circuit) using new current sensing circuit is proposed. This LED driver IC can provide a constant current with high current precision over a wide input voltage range. The proposed current-sensing circuit is composed of a cascode current sensor and a current comparator with only one reference voltage. This IC minimizes the voltage stress of the MOSFET (metal oxide semiconductor field effect transistor) from the maximum input voltage and has low power consumption and chip area by using simple-structured comparator and minimum bias current. To confirm the functioning and characteristics of our proposed LED driver IC, we designed a buck converter. The LED current ripple of the designed IC is in ${\pm}5%$ and a tolerance of the average LED current is lower than 2.43%. This shows much improved feature than the previous method. Also, protections for input voltage and operating temperature are designed to improve the reliability of the designed IC. Designed LED driver IC uses 1.0 ${\mu}m$ X-Fab. BiCMOS process parameters and electrical characteristics and functioning are verified by spectre (Cadence) simulation.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.9-9
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• 2010

In this paper, High Brightness LED driver IC using new current sensing circuit is proposed. This LED driver IC can provide a constant current with high current precision over a wide input voltage range. The proposed current-sensing circuit is composed of a cascode current sensor and a current comparator with only one reference voltage. This IC minimizes the voltage stress of the MOSFET from the maximum input voltage and has low power consumption and chip area by using simple-structured comparator and minimum bias current. The LED current ripple of the designed IC is in ${\pm}5%$ and a tolerance of the average LED current is lower than 2.43%. This shows much improved feature than the previous method. Also, protections for input voltage and operating temperature are designed to improve the reliability of the designed IC. Designed LED driver IC uses $1{\mu}m$ X-Fab. BiCMOS process parameters and electrical characteristics and functioning are verified by spectre(Cadence) simulation.

• 전기학회논문지
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• 제61권11호
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• pp.1752-1757
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• 2012

With the development in industry, power demand has increased rapidly. As consumption of power has increased, Demand for new power line and electric capacity has risen. However, in the event of fault, problems occur in extending the range of fault coverage and increasing fault current. In these reasons, protection devise is recognized as the prevention of an accident and fault current. This paper dealt with minimizing fault propagation and limiting fault current by adjusting fault current limiter (FCL) with fast interrupter. At this point, we compared and analyzed characteristics between non-inductive resistance and fault current which is limited by superconducting units. In normal state of the power system, power was supplied to the load, but when fault occurred, the interrupter was operated as CT which detected the over-current. Its operation made the limitation of fault current through a FCL. We concluded that the limiter using superconducting units was more efficient with the increase of power voltage. Superconducting fault current limiter with the fast interrupter prevented the spread of a fault, and improved reliability of power system.

• 제어로봇시스템학회논문지
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• 제6권8호
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• pp.666-671
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• 2000

With the current advances in optical WDM (Wavelength Division Multiplexing) networking technologies and the increasing demand for network bandwidth the Next Generation Internet is expected to be a network that runs IP(Internet Protocol) directly over WDM-based optical networks. The network control architecture for the IP over WDM networks is different from that of traditional Internet since the underlying WDM devices have more constraints than electronic IP routers such as the lack of optical buffers and wavelength continuity property etc. In this paper we introduce several architectural models for implementing IP over WDM networks and propose an integrated network control framework for the IP over WDM networks. This framework leverages the traffic engineering control architecture for the MPLS (Multi-Protocol Label Switching) networks and is mainly developed for the IP over packet-switched WDM networks. We also report several preliminary simulation results of contention resolution schemes in the packet-switched WDM networks.

• International journal of advanced smart convergence
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• 제9권3호
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• pp.253-259
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• 2020

Most of today's large-scale cloud systems and enterprise data centers are distributing resources to improve scalability and resource utilization. NVMe-over-Fabric protocol allows submitting NVMe commands to a remote NVMe SSD through RDMA (Remote Direct Memory Access) network. It is attracting attention recently because it is possible to construct a disaggregation storage system with low latency through the protocol. However, the current I/O stack of NVMe-over-Fabric has an inefficient structure for maintaining compatibility with the traditional I/O stack. Therefore, in this paper, we propose a new mechanism to reduce I/O latency and CPU overhead by modifying I/O path of NVMe-over-Fabric to pass through legacy block layer. According to the performance evaluation results, the proposed mechanism is able to reduce the I/O latency and CPU overhead by up to 22% and 24% compared to the existing NVMe-over-Fabrics protocol, respectively.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1990년도 추계학술대회 논문집 학회본부
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• pp.73-77
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• 1990

In this paper we describe the solid-state ac-circuit breaker which has the characteristic of both a half cycle circuit breaker and a current limiting circuit breaker. This circuit breaker has a current limiting resistor in order to surprises the fault current to a certain level and discharge the energe included in circuit inductor. We explain the effect of circuit parameter on transient phenomena of switch device by using EMTP and finally design the control circuit consisted synchronous closing circuit, over- current detecting circuit and sensing circuit of rate of rise of fault current.