• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.5
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• pp.94-103
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• 1997

It is necesary that analog buffer circuit should drive an external load in the VLSI design such as switched capacitor efilter (SCF), D/A converter, A/d converter, telecommunicatin circuit, etc. The conventional CMOS buffer circuit have many probvlems according as CMOS technique. Firstly, Capacity of large load ar enot able to opeate well. The problem can be solve to use class AB stages. But large load are operated a difficult, because an element of existing CMOS has a quadratic functional relation with inptu and outut voltage versus output current. Secondly, whole circuit of dynamic rang edecrease, because a range of inpt and output voltages go down according as increasing of intergration rate drop supply voltage. In this paper suggests that new differential CMOS line driver make out of operating an external of large load. In telecommunication's chip case transmission line could be a load. It is necessary that a load operate line driver. The proposal circuit is planned to hav ea high generation power rnage of voltage with preservin linearity. And circuit of capability is inspected through simulation program (HSPICE).

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.629-631
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• 2004

The proposed output buffer is presented for driving large-size LCD panels. This output buffer is designed by adding some simple circuitry to the conventional two-stage operational amplifier. The proposed circuit is simulated in a high-voltage 0.35um CMOS process with HSPICE. The simulated result is more improved settling time than that of conventional one.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.10
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• pp.1513-1517
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• 2012

As demands for green industry increase, this paper proposes a power control technique that can substitute pre -existing CCFL(Cold Cathode Fluorescent Lamp) and optimize power consumption of LED BLU. This technique is designing LED driver circuit that make a DC-DC output voltage(VLED) to have a linear control function for a supply voltage of LED string. The proposed LED driver have an advantage that can increase or decrease a DC-DC output voltage compared with conventional LED driver. The designed LED driver circuit was designed using 0.35um CMOS technology. And its operation was verified through simulation.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.27 no.2
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• pp.22-28
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• 2013

In this paper, the low cost SOA Dimming Driver which consisted of LabVIEW programming part capable of current pattern design, DAQ module for analog voltage output, and voltage to current converter has realized. The output current(possible to 3A) from the Driver was clearly constant without ripple and also showed no variance until 1mA unit for a long time operation. The proposed low cost Driver can replace the previous high cost SOA Drivers for wavelength swept lasers fully and provide the convenience and safety of auto-supplying a designed current pattern.

• Journal of Korea Society of Industrial Information Systems
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• v.20 no.6
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• pp.29-36
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• 2015

This paper presents an LED backlight driver IC consisting of three linear current regulators and an output-voltage regulation loop with a self-adjustable reference voltage. In the proposed LED driver, the output voltage is controlled by dual feedback loops. The first loop senses and controls the output voltage, and the second loop senses the voltage drop of the linear current regulator and adjusts the reference voltage. With these feedback loops, the voltage drop of the linear current regulator is maintained at a minimum value, at which the driver efficiency is maximized. The output of the driver is a three-channel LED setup with four LEDs in each channel. The luminance is adjusted by the PWM dimming signal. The proposed driver is designed by a $0.35-{\mu}m$ 60-V high-voltage process, resulting in an experimental maximum efficiency of approximately 85%.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.883-884
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• 2004

High-speed IC for time-division multiplexing (TDM) optical transmission systems have been designed and fabricated by using InP heterojunction-bipolar-transistor (HBT) technology. The driver IC was developed for driving external modulators, featuring differential outputs and the operation speed up to 10 Gbps with an output voltage swing of 1.3 Vpp at each output which was the limit of the measurement. Because -3 dB frequency was 20GHz, this circuit will be operated up to 20Gbps. 1.3Vpp differential output was achieved by switching 50 mA into a 50 $\Omega$ load. The power dissipation of the driver IC was 1W using a single supply voltage of -3.5Y. Input md output return loss of the IC were better than 10 dB and 15 dB, respectively, from DC to 20GHz. The chip size of fabricated IC was $1.7{\Box}1.2 mm^{2}$.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.567-570
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• 2002

The LVDS (Low Voltage Differential Signaling) I/O cells, fully compatible with ANSI TIA/ EIA-644 LVDS standard, are designed using a 0.35${\mu}m$ standard CMOS technology. With a single 3V supply, the core cells operate at 1.34Gbps and power consumption of the output driver and the input receiver is 10. 5mW and 4.2mW, respectively. In the output driver, we employ the DCMFB (Dynamic Common-Mode FeedBack) circuit which can control the DC offset voltage of differential output signals. The SPICE simulation result of the proposed output driver shows that the variation of the DC offset voltage is 15.6% within a permissible range. In the input receiver, the proposed dual input stage with a positive feedback latch covers rail-to-rail input common-mode range and enables a high-speed, low-power operation. 5-channels of the proposed LVDS I/O pair can handle display data up to 8-bit gray scale and UXGA resolution.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.7-13
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• 2008

This paper proposes a newly structured circuit that can compensate current deviation of a data driver circuit for OLED. A conventional data drivel circuit for OLED cannot compensate the current deviation at the data drivel circuit output terminal generated by MOS process change, but the proposed data drivel circuit can authorize uniform value of current to an OLED panel by calibrating the current deviation at the output terminal. The proposed circuit can minimize current deviation of the output current via process change by connecting the circuit for data output current with a common interconnect line through addition of a switching transistor to the existing data output circuit. The circuit proposed in this paper has been designed based on an OLED panel supporting $128{\times}128$ resolution, and the process used for driver circuit development is 0.35um. As a result of the experiment in this study, the output current of the data driver circuit proposed here has 1% range of error, while 9% range of severe changes was demonstrated in the case of the previous data driver circuit. When using the data driver circuit for OLED proposed in this paper, high definition OLED display can be actualized and the circuit can be applied to mobile display devices requiring high quality display features.

• Journal of the Semiconductor & Display Technology
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• v.5 no.1 s.14
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• pp.33-38
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• 2006

The ATE driver to test a high speed semiconductor chip is designed by using general logic drivers instead of dedicated pin drivers. We have proposed a structure of general logic drivers using FPCA and assured its correct operation by EDA tool simulation. PCB circuit was implemented and Altera FPGA chip was programmed using DDR I/O library. On the PCB, it is necessary to place two resistors connected output drivers near to the output pin to adjust an impedance matching. We confirmed that the measured results agree with the simulated values within 5% errors at room temperature for the input signals with 800Mbps data transfer rate and 1.8V operating voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.8
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• pp.54-61
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• 2001

A fully on-chip open-drain CMOS output driver was designed for high bandwidth DRAMs, such that its output voltage swing was insensitive to the variations of temperature and supply voltage. An auto refresh signal was used to update the contents of the current control register, which determined the transistors to be turned-on among the six binary-weighted transistors of an output driver. Because the auto refresh signal is available in DRAM chips, the output driver of this work does not require any external signals to update the current control register. During the time interval while the update is in progress, a negative feedback loop is formed to maintain the low level output voltage ($V_OL$) to be equal to the reference voltage ($V_{OL.ref}$) which is generated by a low-voltage bandgap reference circuit. Test results showed the successful operation at the data rate up to 1Gb/s. The worst-case variations of $V_{OL.ref}$ and $V_OL$ of the proposed output driver were measured to be 2.5% and 7.5% respectively within a temperature range of $20^{\circ}C$ to $90^{\circ}C$ and a supply voltage range of 2.25V to 2.75V, while the worst-case variation of $V_OL$ of the conventional output driver was measured to be 24% at the same temperature and supply voltage ranges.