• Journal of Navigation and Port Research
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• v.29 no.1 s.97
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• pp.23-28
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• 2005

The signal in wireless multi-path channel is affected by fading and ISI because of high data rate transmission, so the signal has the high error rate. The present modulation and demodulation method of DSRC system can not expect sufficient for providing data service over 1 Mbps, so the channel equalization and advanced modulation and demodulation methods are required. OFDM is generally known as an effective technique for high data rate transmission system, since it can prevent ISI by inserting a guard interval. However, a guard interval longer than channel delay spread has to be used in each OFDM symbol period, thus resulting a considerable loss in the efficiency of channel utilization Therefore the equalizer is necessary to cancel ISI to accommodate advanced ITS service with higher bit rate and longer channel delay spread condition In this paper, the channel equalizer for the OFDM -DSRC system was designed and its performance in a multi-path fading environment was evaluated with computer simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11A
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• pp.1263-1270
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• 2004

A low-power 64-point FFT/IFFT processor core is designed, which is an essential block in OFDM-based wireless LAM modems. The radix-2/418 DIF (Decimation-ln-Frequency) FFT algorithm is implemented using R2SDF (Radix-2 Single-path Delay Feedback) structure. Some design techniques for low-power implementation are considered from algorithm level to circuit level. Based on the analysis on infernal data flow, some unnecessary switching activities have been eliminated to minimize power dissipation. In circuit level, constant multipliers and complex-number multiplier in data-path are designed using truncation structure to reduce gate counts and power dissipation. The 64-point FFT/IFFT core designed in Verilog-HDL has about 28,100 gates, and timing simulation results using gate-level netlist with extracted SDF data show that it can safely operate up to 50-MHz＠2.5-V, resulting that a 64-point FFT/IFFT can be computed every 1.3-${\mu}\textrm{s}$. The functionality of the core was fully verified by FPGA implementation using various test vectors. The average SQNR of over 50-dB is achieved, and the average power consumption is about 69.3-mW with 50-MHz＠2.5-V.