• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.375-375
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• 2010

CdTe as an absorber material is widely used in thin film solar cells with the heterostructure due to its almost ideal band gap energy of 1.45 eV, high photovoltaic conversion efficiency, low cost and stable performance. The deposition methods and preparation conditions for the fabrication of CdTe are very important for the achievement of high solar cell conversion efficiency. There are some rearranged reports about the deposition methods available for the preparation of CdTe thin films such as close spaced sublimation (CSS), physical vapor deposition (PVD), vacuum evaporation, vapor transport deposition (VTD), closed space vapor transport, electrodeposition, screen printing, spray pyrolysis, metalorganic chemical vapor deposition (MOCVD), and RF sputtering. The RF sputtering method for the preparation of CdTe thin films has important advantages in that the thin films can be prepared at low growth temperatures with large-area deposition suitable for mass-production. The authors reported that the optical and electrical properties of CdTe thin film were closely connected by the thickness-uniformity of the film in the previous study [1], which means that the better optical absorbance and the higher carrier concentration could be obtained in the better condition of thickness-uniformity for CdTe thin film. The thickness-uniformity could be controlled and improved by the some process parameters such as vacuum level and RF power in the sputtering process of CdTe thin films. However, there is a limitation to improve the thickness-uniformity only in the preparation process [1]. So it is necessary to introduce the external or additional method for improving the thickness-uniformity of CdTe thin film because the cell size of thin film solar cell will be enlarged. Therefore, the authors firstly applied the chemical mechanical polishing (CMP) process to improving the thickness-uniformity of CdTe thin films with a G&P POLI-450 CMP polisher [2]. CMP process is the most important process in semiconductor manufacturing processes in order to planarize the surface of the wafer even over 300 mm and to form the copper interconnects with damascene process. Some important CMP characteristics for CdTe were obtained including removal rate (RR), WIWNU%, RMS roughness, and peak-to-valley roughness [2]. With these important results, the CMP process for CdTe thin films was performed to improve the thickness-uniformity of the sputtering-deposited CdTe thin film which had the worst two thickness-uniformities of them. Some optical properties including optical transmittance and absorbance of the CdTe thin films were measured by using a UV-Visible spectrophotometer (Varian Techtron, Cary500scan) in the range of 400 - 800 nm. After CMP process, the thickness-uniformities became better than that of the best condition in the previous sputtering process of CdTe thin films. Consequently, the optical properties were directly affected by the thickness-uniformity of CdTe thin film. The absorbance of CdTe thin films was improved although the thickness of CdTe thin film was not changed.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.308-309
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• 2012

One of the critical issues in the growth of multijunction solar cell is the formation of a highly doped Esaki interband tunnel diode which interconnects unit cells of different energy band gap. Small electrical and optical losses are the requirements of such tunnel diodes [1]. To satisfy these requirements, tens of nanometer thick gallium arsenide (GaAs) can be a proper candidate due to its high carrier concentration in low energy band gap. To obtain highly doped GaAs in molecular beam epitaxy, the temperatures of Si Knudsen cell (K-cell) for n-type GaAs and Be K-cell for p-type GaAs were controlled during GaAs epitaxial growth, and the growth rate is set to 1.75 A/s. As a result, the doping concentration of p-type and n-type GaAs increased up to $4.7{\times}10^{19}cm^{-3}$ and $6.2{\times}10^{18}cm^{-3}$, respectively. However, the obtained n-type doping concentration is not sufficient to form a properly operating tunnel diode which requires a doping concentration close to $1.0{\times}10^{19}cm^{-3}$ [2]. To enhance the n-type doping concentration, n-doped GaAs samples were grown with a lower growth rate ranging from 0.318 to 1.123 A/s at a Si K-cell temperature of $1,180^{\circ}C$. As shown in Fig. 1, the n-type doping concentration was increased to $7.7{\times}10^{18}cm^{-3}$ when the growth rate was decreased to 0.318 A/s. The p-type doping concentration also increased to $4.1{\times}10^{19}cm^{-3}$ with the decrease of growth rate to 0.318 A/s. Additionally, bulk resistance was also decreased in both the grown samples. However, a transmission line measurement performed on the n-type GaAs sample grown at the rate of 0.318 A/s showed an increased specific contact resistance of $6.62{\times}10^{-4}{\Omega}{\cdot}cm^{-2}$. This high value of contact resistance is not suitable for forming contacts and interfaces. The increased resistance is attributed to the excessively incorporated dopant during low growth rate. Further studies need to be carried out to evaluate the effect of excess dopants on the operation of tunnel diode.

• Journal of the Korea Convergence Society
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• v.8 no.8
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• pp.9-15
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• 2017

With the development of semiconductor integration technology, central processing units and storage devices have been miniaturized and performance has been rapidly developed, interconnection network technology is becoming a more important factor in terms of the performance of high performance computing system. In this paper, we analyze the trend of interconnection network technology used in high performance computing. Interconnect technology, which is the most widely used in the Supercomputer Top 500(2017. 06.), is an Infiniband. Recently, Ethernet is the second highest share after InfiniBand due to the emergence of 40/100Gbps Gigabit Ethernet technology. Gigabit Ethernet, where latency performance is lower than InfiniBand, is preferred in cost-effective medium-sized data centers. In addition, top-end HPC systems that demand high performance are devoting themselves from Ethernet and InfiniBand technologies and are attempting to maximize system performance by introducing their own interconnect networks. In the future, high-performance interconnects are expected to utilize silicon-based optical communication technology to exchange data with light.

• Korean Chemical Engineering Research
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• v.45 no.5
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• pp.466-472
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• 2007

A technology platform for wafer-level three-dimensional integration circuits (3D-ICs) is presented, and that uses wafer bonding with low-k polymeric adhesives and Cu damascene inter-wafer interconnects. In this work, one of such technical platforms is explained and characterized using a test vehicle of inter-wafer 3D via-chain structures. Electrical and mechanical characterizations of the structure are performed using continuously connected 3D via-chains. Evaluation results of the wafer bonding, which is a necessary process for stacking the wafers and uses low-k dielectrics as polymeric adhesive, are also presented through the wafer bonding between a glass wafer and a silicon wafer. After wafer bonding, three evaluations are conducted; (1) the fraction of bonded area is measured through the optical inspection, (2) the qualitative bond strength test to inspect the separation of the bonded wafers is taken by a razor blade, and (3) the quantitative bond strength is measured by a four point bending. To date, benzocyclobutene (BCB), $Flare^{TM}$, methylsilsesquioxane (MSSQ) and parylene-N were considered as bonding adhesives. Of the candidates, BCB and $Flare^{TM}$ were determined as adhesives after screening tests. By comparing BCB and $Flare^{TM}$, it was deduced that BCB is better as a baseline adhesive. It was because although wafer pairs bonded using $Flare^{TM}$ has a higher bond strength than those using BCB, wafer pairs bonded using BCB is still higher than that at the interface between Cu and porous low-k interlevel dielectrics (ILD), indicating almost 100% of bonded area routinely.